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PDF MQ82C55A Data sheet ( Hoja de datos )
| Número de pieza | MQ82C55A | |
| Descripción | CMOS Programmable Peripheral Interface | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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Data Sheet
MS82C55A, MQ82C55A, MP82C55A
June 15, 2006
FN6140.2
CMOS Programmable Peripheral Interface
The Intersil 82C55A is a high performance CMOS version of
the industry standard 8255A and is manufactured using a
self-aligned silicon gate CMOS process (Scaled SAJI IV).
The MX82C55A has identical features as the X82C55 with
the exception of no bus hold devices on the port pins. It is a
general purpose programmable I/O device which may be
used with many different microprocessors. There are 24 I/O
pins which may be individually programmed in two groups of
www.DataShe1e2t4aUn.dcoumsed in three major modes of operation. The high
performance and industry standard configuration of the
82C55A make it compatible with the 80C86, 80C88 and
other microprocessors.
Static CMOS circuit design insures low operating power. The
Intersil advanced SAJI process results in performance equal
to or greater than existing functionally equivalent products at
a fraction of the power.
Ordering Information
PART
NUMBERS *
(Note)
PART
TEMP. PACKAGE
MARKING RANGE (°C) (Pb-free)
PKG.
DWG. #
CMP82C55AZ CMP82C55AZ 0 to 70 40 Ld PDIP** E40.6
CMS82C55AZ CMS82C55AZ 0 to 70 44 Ld PLCC N44.65
IMS82C55AZ IMS82C55AZ -40 to 85
CMQ82C55AZ CMQ82C55AZ 0 to 70 44 Ld MQFP Q44.10x10
IMQ82C55AZ IMQ82C55AZ -40 to 85
*Add “96” suffix to part number for tape and reel packaging.
**Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Features
• Pb-Free Plus Anneal Available (RoHS Compliant)
(See Ordering Info)
• Pin Compatible with OKI MSM82C55A
- No Bus Hold Devices on any Port Pins
• 24 Programmable I/O Pins
• Fully TTL Compatible
• High Speed, No “Wait State” Operation with 8MHz 80C86
and 80C88
• Direct Bit Set/Reset Capability
• Enhanced Control Word Read Capability
• L7 Process
• 2.5mA Drive Capability on All I/O Ports
• Low Standby Power (ICCSB) . . . . . . . . . . . . . . . . . . .10µA
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
MS82C55A, MQ82C55A, MP82C55A
Operational Description
Mode Selection
There are three basic modes of operation than can be
selected by the system software:
Mode 0 - Basic Input/Output
Mode 1 - Strobed Input/Output
Mode 2 - Bidirectional Bus
When the reset input goes “high”, all ports will be set to the
input mode. After the reset is removed, the 82C55A can
remain in the input mode with no additional initialization
required. The control word register will contain 9Bh. During
the execution of the system program, any of the other modes
may be selected using a single output instruction. This
www.DataSheaellto4wU.scoamsingle 82C55A to service a variety of peripheral
devices with a simple software maintenance routine. Any
port programmed as an output port is initialized to all zeros
when the control word is written.
ADDRESS BUS
CONTROL BUS
DATA BUS
RD, WR
MODE 0
B
D7-D0
82C55A
C
A0-A1
CS
A
8 I/O 4 I/O 4 I/O 8 I/O
PB7-PB0 PC3-PC0 PC7-PC4 PA7-PA0
MODE 1
C
BA
8 I/O
8 I/O
PB7-PB0 CONTROL CONTROL PA7-PA0
OR I/O OR I/O
MODE 2
B
8 I/O
C
A
BI-
DIRECTIONAL
PB7-PB0
CONTROL
PA7-PA0
FIGURE 3. BASIC MODE DEFINITIONS AND BUS INTERFACE
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
GROUP B
PORT C (LOWER)
1 = INPUT
0 = OUTPUT
PORT B
1 = INPUT
0 = OUTPUT
MODE SELECTION
0 = MODE 0
1 = MODE 1
GROUP A
PORT C (UPPER)
1 = INPUT
0 = OUTPUT
PORT A
1 = INPUT
0 = OUTPUT
MODE SELECTION
00 = MODE 0
01 = MODE 1
1X = MODE 2
MODE SET FLAG
1 = ACTIVE
FIGURE 4. MODE DEFINITION FORMAT
The modes for Port A and Port B can be separately defined,
while Port C is divided into two portions as required by the
Port A and Port B definitions. All of the output registers,
including the status flip-flops, will be reset whenever the
mode is changed. Modes may be combined so that their
functional definition can be “tailored” to almost any I/O
structure. For instance: Group B can be programmed in
Mode 0 to monitor simple switch closings or display
computational results, Group A could be programmed in
Mode 1 to monitor a keyboard or tape reader on an interrupt-
driven basis.
The mode definitions and possible mode combinations may
seem confusing at first, but after a cursory review of the
complete device operation a simple, logical I/O approach will
surface. The design of the 82C55A has taken into account
things such as efficient PC board layout, control signal definition
vs. PC layout and complete functional flexibility to support
almost any peripheral device with no external logic. Such
design represents the maximum use of the available pins.
Single Bit Set/Reset Feature (Figure 5)
Any of the eight bits of Port C can be Set or Reset using a
single Output instruction. This feature reduces software
requirements in control-based applications.
When Port C is being used as status/control for Port A or B,
these bits can be set or reset by using the Bit Set/Reset
operation just as if they were output ports.
5 FN6140.2
June 15, 2006
5 Page 
WR
OBF
INTR
ACK
OUTPUT
www.DataSheet4U.com
MS82C55A, MQ82C55A, MP82C55A
tWOB
tAOB
tWIT
tAK
tWB
FIGURE 9. MODE 1 (STROBED OUTPUT)
tAIT
PA7-PA0 8
PA7-PA0 8
CONTROL WORD
RD
D7 D6 D5 D4 D3 D2 D1 D0
1 0 1 1 1/0 1 0
PC6, PC7
1 = INPUT
0 = OUTPUT
WR
PC4
PC5
PC3
PC6, PC7
PB7, PB0
PC1
PC2
PC0
STBA
IIBFA
INTRA
2
I/O
8
OBFB
ACKB
INTRB
CONTROL WORD
WR
D7 D6 D5 D4 D3 D2 D1 D0
1 0 1 0 1/0 1 1
PC4, PC5
1 = INPUT
0 = OUTPUT
RD
PC7
PC6
PC3
PC4, PC5
OBFA
ACKA
INTRA
2
I/O
PB7, PB0
PC2
PC1
PC0
8
STBB
IBFB
INTRB
PORT A - (STROBED INPUT)
PORT B - (STROBED OUTPUT)
PORT A - (STROBED OUTPUT)
PORT B - (STROBED INPUT)
Combinations of Mode 1: Port A and Port B can be individually defined as input or output in Mode 1 to support a wide variety of strobed I/O applications.
FIGURE 10. COMBINATIONS OF MODE 1
Operating Modes
Mode 2 (Strobed Bidirectional Bus I/O)
This functional configuration provides a means for
communicating with a peripheral device or structure on a
single 8-bit bus for both transmitting and receiving data
(bidirectional bus I/O). “Hand shaking” signals are provided to
maintain proper bus flow discipline similar to Mode 1. Interrupt
generation and enable/disable functions are also available.
Mode 2 Basic Functional Definitions:
• Used in Group A only
• One 8-bit, bidirectional bus Port (Port A) and a 5-bit
control Port (Port C)
• Both inputs and outputs are latched
• The 5-bit control port (Port C) is used for control and
status for the 8-bit, bidirectional bus port (Port A)
Bidirectional Bus I/O Control Signal Definition
(Figures 11, 12, 13, 14)
INTR - (Interrupt Request). A high on this output can be
used to interrupt the CPU for both input or output operations.
Output Operations
OBF - (Output Buffer Full). The OBF output will go “low” to
indicate that the CPU has written data out to port A.
ACK - (Acknowledge). A “low” on this input enables the three-
state output buffer of port A to send out the data. Otherwise,
the output buffer will be in the high impedance state.
INTE 1 - (The INTE flip-flop associated with OBF).
Controlled by bit set/reset of PC4.
Input Operations
STB - (Strobe Input). A “low” on this input loads data into the
input latch.
IBF - (Input Buffer Full F/F). A “high” on this output indicates
that data has been loaded into the input latch.
INTE 2 - (The INTE flip-flop associated with IBF). Controlled
by bit set/reset of PC4.
11 FN6140.2
June 15, 2006
11 Page | ||
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