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ISL12020 데이터시트 PDF




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기능 Low Power RTC
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ISL12020 데이터시트, 핀배열, 회로
ISL12020
®
Real Time Clock with On Chip Temp Compensation ±5ppm
Data Sheet
March 29, 2007
FN6450.0
Low Power RTC with VDD Battery Backed
SRAM and Embedded Temp
Compensation ±5ppm with Auto Day Light
Saving
The ISL12020 device is a low power real time clock with an
embedded Temp sensor for oscillator compensation,
clock/calendar, power fail, low battery monitor, brown out
indicator, single periodic or polled alarms, intelligent battery
backup switching and 128 bytes of battery-backed user
SRAM.
The oscillator uses an external, low-cost 32.768kHz crystal.
The real time clock tracks time with separate registers for
hours, minutes, and seconds. The device has calendar
registers for date, month, year and day of the week. The
calendar is accurate through 2099, with automatic leap year
correction.
Daylight Savings time adjustment is done automatically,
using parameters entered by the user. Power fail and battery
monitors offer user-selectable trip levels. A time stamp
function records the time and date of switchover from VDD to
battery power, and also from battery to VDD power.
Pinoutwww.DataSheet4U.com
ISL12020
(8 LD SOIC)
TOP VIEW
X1
X2
VBAT
GND
1
2
3
4
8 VDD
7 IRQ/FOUT
6 SCL
5 SDA
Features
• Real Time Clock/Calendar
- Tracks Time in Hours, Minutes and Seconds
- Day of the Week, Day, Month and Year
• On-chip Oscillator Compensation Over the Operating
Temp Range
- ±5ppm over -20°C to +70°C
• Day Light Saving Time
- Customer Programmable
• 15 Selectable Frequency Outputs
• 1 Alarm
- Settable to the Second, Minute, Hour, Day of the Week,
Day, or Month
- Single Event or Pulse Interrupt Mode
• Automatic Backup to Battery or Super Cap
- Operation to VBAT = 1.8V
- 1.0µA Battery Supply Current
• Battery Status Monitor, 2 Levels, Selectable by Customer
to:
- Seven Selectable Voltages for Each Level
• Power Status Brown Out Monitor
• Six Selectable Trip Level, from 4.675V to 2.295V Power
Failure Detection
• Time Stamp during Power to Battery and Battery to Power
Cross Over
- Time Stamp. First VDD to VBAT, and Last VBAT to VDD
• 128 Bytes Battery-Backed User SRAM
• I2C Interface
- 400kHz Clock Frequency
• 8 Ld SOIC Package ISL12020
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Utility Meters
• POS Equipment
• Medical Application
• Security Related Application
• Vending Machine
• White Goods
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.




ISL12020 pdf, 반도체, 판매, 대치품
ISL12020
I2C Interface Specifications Test Conditions: VDD=+2.7 to +5.5V, Temperature = -20°C to +70°C, unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
TYP
MIN (Note 7) MAX UNITS NOTES
VIL SDA and SCL input buffer LOW
voltage
-0.3 0.3 x VDD V
VIH SDA and SCL Input Buffer HIGH
Voltage
0.7 x VDD
VDD + 0.3 V
Hysteresis
SDA and SCL Input Buffer
Hysteresis
0.05 x VDD
V
VOL SDA Output Buffer LOW Voltage, VDD = 5V, IOL = 3mA
Sinking 3mA
0.4 V
CPIN
fSCL
tIN
SDA and SCL Pin Capacitance
SCL Frequency
TA = +25°C, f = 1MHz,
VDD = 5V, VIN = 0V,
VOUT = 0V
Pulse Width Suppression Time at Any pulse narrower than the
SDA and SCL Inputs
max spec is suppressed.
10 pF
400 kHz
50 ns
tAA SCL Falling Edge To SDA Output SCL falling edge crossing
Data Valid
30% of VDD, until SDA exits
the 30% to 70% of VDD
window.
900 ns
tBUF
Time the Bus Must be Free Before
The Start of a New Transmission
SDA crossing 70% of VDD
during a STOP condition, to
SDA crossing 70% of VDD
during the following START
condition.
1300
ns
tLOW
Clock LOW Time
Measured at the 30% of VDD
crossing.
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VDD
crossing.
600
ns
tSU:STA
START Condition Setup Time
tHD:STA
START Condition Hold Time
tSU:DAT
Input Data Setup Time
tHD:DAT
Input Data Hold Time
tSU:STO
STOP Condition Setup Time
tHD:STO
STOP Condition Hold Time
SCL rising edge to SDA
falling edge. Both crossing
70% of VDD.
From SDA falling edge
crossing 30% of VDD to SCL
falling edge crossing 70% of
VDD.
From SDA exiting the 30% to
70% of VDD window, to SCL
rising edge crossing 30% of
VDD.
From SCL falling edge
crossing 30% of VDD to SDA
entering the 30% to 70% of
VDD window.
From SCL rising edge
crossing 70% of VDD, to SDA
rising edge crossing 30% of
VDD.
From SDA rising edge to
SCL falling edge. Both
crossing 70% of VDD.
600
600
100
0
600
600
ns
ns
ns
900 ns
ns
ns
4 FN6450.0
March 29, 2007

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ISL12020 전자부품, 판매, 대치품
ISL12020
EQUIVALENT AC OUTPUT LOAD CIRCUIT FOR VDD = 5V
5.0V
SDA
AND
IRQ/FOUT
1533Ω
FOR VOL= 0.4V
AND IOL = 3mA
100pF
FIGURE 1. STANDARD OUTPUT LOAD FOR TESTING THE
DEVICE WITH VDD = 5.0V
General Description
The ISL12020 devices are low power real time clocks
(RTCs) with embedded temperature sensors. They contain
crystal frequency compensation circuitry over the operating
temperature range, clock/calendar, power fail and low
battery monitors, brown out indicator with separate
(LVRSET) reset pin (ISL12021 only), 1 periodic or polled
alarm, intelligent battery backup switching and 128 Bytes of
battery-backed user SRAM.
The oscillator uses an external, low cost 32.768kHz crystal.
The real time clock tracks time with separate registers for
hours, minutes and seconds. The device has calendar
registers for date, month, year and day of the week. The
calendar is accurate through 2099, with automatic leap year
correction. In addition, both the ISL12020 could be
programmed for automatic Daylight Saving Time (DST)
adjustment by entering local DST information.
The ISL1202x’s alarm can be set to any clock/calendar value
for a match. For example, every minute, every Tuesday or at
5:23 AM on March 21. The alarm status is available by
checking the Status Register, or the device can be
configured to provide a hardware interrupt via the IRQ pin.
There is a repeat mode for the alarm allowing a periodic
interrupt every minute, every hour, every day, etc.
The device also offers a backup power input pin. This VBAT
pin allows the device to be backed up by battery or Super
Cap with automatic switchover from VDD to VBAT. The
ISL12020 devices are specified for VDD = 2.7V to 5.5V and
the clock/calendar portion of the device remains fully
operational in battery backup mode down to 1.8V (Standby
Mode). The VBAT level is monitored and reported against
preselected levels. The first report is registered when the
VBAT level falls below 85% of nominal level, the second level
is set for 75%. Battery levels are stored in VBATM registers.
The ISL12020 offers a “Brown Out” alarm once the VDD
falls below a pre-selected trip level. In the ISL12020, this
allows system Micro to save vital information to memory
before complete power loss. There are six VDD levels that
could be selected for initiation of brown out alarm.
Pin Descriptions
X1, X2
The X1 and X2 pins are the input and output, respectively, of
an inverting amplifier. An external 32.768kHz quartz crystal
is used with the device to supply a timebase for the real time
clock. Internal compensation circuitry with internal
temperature sensor provides frequency corrections for
selected popular crystals to ±5ppm over the operating
temperature range from -40°C to +85°C. (See “Application
Section” on page 22 for recommended crystal). ISL12020
allows the user to input via I2C serial bus the temperature
variation profile of crystals not listed in the “Application
Section” on page 22. This oscillator compensation network
can also be used to calibrate the initial crystal timing
accuracy at room temperature. The device can also be
driven directly from a 32.768kHz source at pin X1.
X1
X2
FIGURE 2. RECOMMENDED CRYSTAL CONNECTION
VBAT
This input provides a backup supply voltage to the device.
VBAT supplies power to the device in the event that the VDD
supply fails. This pin can be connected to a battery, a Super
Capacitor or tied to ground if not used. See the Battery
Monitor parameter in the DC Operating Characteristics-RTC
on page 3.
IRQ/FOUT (Interrupt Output/Frequency Output)
This dual function pin can be used as an interrupt or
frequency output pin. The IRQ/FOUT mode is selected via
the frequency out control bits of the control/status register.
Interrupt Mode. The pin provides an interrupt signal
output. This signal notifies a host processor that an alarm
has occurred and requests action. It is an open drain
active low output.
Frequency Output Mode. The pin outputs a clock signal
which is related to the crystal frequency. The frequency
output is user selectable and enabled via the I2C bus. It is
an open drain output.
Serial Clock (SCL)
The SCL input is used to clock all serial data into and out of
the device. The input buffer on this pin is always active (not
gated). It is disabled when the backup power supply on the
VBAT pin is activated to minimize power consumption.
7 FN6450.0
March 29, 2007

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