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ISL12021 데이터시트 PDF




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부품번호 ISL12021 기능
기능 Real Time Clock
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ISL12021 데이터시트, 핀배열, 회로
ISL12021
®
Real Time Clock with On Chip Temp Compensation ±5ppm
Data Sheet
March 30, 2007
FN6451.0
Low Power RTC with VDD Battery Backed
SRAM and Embedded Temp
Compensation ±5ppm with Auto Day Light
Saving
The ISL12021 device is a low power real time clock with an
embedded Temp sensor for oscillator compensation,
clock/calendar, power fail, low battery monitor, brown out
indicator, single periodic or polled alarms, intelligent battery
backup switching and 128 bytes of battery-backed user
SRAM.
The oscillator uses an external, low-cost 32.768kHz crystal.
The real time clock tracks time with separate registers for
hours, minutes, and seconds. The device has calendar
registers for date, month, year and day of the week. The
calendar is accurate through 2099, with automatic leap year
correction.
Daylight Savings time adjustment is done automatically,
using parameters entered by the user. Power fail and battery
monitors offer user-selectable trip levels. A time stamp
function records the time and date of switchover from VDD to
battery power, and also from battery to VDD power.
Pinoutwww.DataSheet4U.com
ISL12021
(14 LD TSSOP)
TOP VIEW
NC
X1
X2
VBAT
GND
LVRST
NC
1
2
3
4
5
6
7
14 NC
13 VDD
12 IRQ
11 SCL
10 SDA
9 FOUT
8 NC
Features
• Real Time Clock/Calendar
- Tracks Time in Hours, Minutes and Seconds
- Day of the Week, Day, Month and Year
• On-chip Oscillator Compensation Over the Operating
Temp Range
- ±5ppm over -20°C to +70°C
• Day Light Saving Time
- Customer Programmable
• Separate FOUT pin
- 15 Selectable Frequency Outputs
• 1 Alarm
- Settable to the Second, Minute, Hour, Day of the Week,
Day, or Month
- Single Event or Pulse Interrupt Mode
- Dedicated IRQ output pin
• Automatic Backup to Battery or Super Cap
- Operation to VBAT = 1.8V
- 1.0µA Battery Supply Current
• Battery Status Monitor, 2 Levels, Selectable by Customer
to:
- Seven Selectable Voltages for Each Level
• Power status Brown Out Monitor
- Six selectable trip level, from 4.675V to 2.295V
- Separate Low Voltage LVRST pin
• Time Stamp during Power to Battery and Battery to Power
Cross Over
- Time Stamp. First VDD to VBAT, and Last VBAT to VDD
• 128 Bytes Battery-Backed User SRAM
• I2C Interface
- 400kHz Clock Frequency
• 14 Ld TSSOP package
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Utility Meters
• POS Equipment
• Medical Application
• Security Related Application
• Vending Machine
• White Goods
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.




ISL12021 pdf, 반도체, 판매, 대치품
ISL12021
I2C Interface Specifications Test Conditions: VDD = +2.7 to +5.5V, Temperature = -20°C to +70°C, unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
TYP
MIN
(Note 7)
MAX
UNITS NOTES
VIL SDA and SCL input buffer LOW
voltage
-0.3
0.3 x VDD
V
VIH SDA and SCL Input Buffer HIGH
Voltage
0.7 x VDD
VDD + 0.3
V
Hysteresis SDA and SCL Input Buffer
Hysteresis
0.05 x VDD
V
VOL SDA Output Buffer LOW Voltage, VDD = 5V, IOL = 3mA
Sinking 3mA
0.4 V
CPIN
fSCL
tIN
SDA and SCL Pin Capacitance
SCL Frequency
Pulse Width Suppression Time at
SDA and SCL Inputs
TA = +25°C, f = 1MHz,
VDD = 5V, VIN = 0V,
VOUT = 0V
Any pulse narrower than the
max spec is suppressed.
10 pF
400 kHz
50 ns
tAA
tBUF
SCL Falling Edge To SDA Output
Data Valid
Time the Bus Must be Free Before
The Start of a New Transmission
SCL falling edge crossing 30%
of VDD, until SDA exits the
30% to 70% of VDD window.
SDA crossing 70% of VDD
during a STOP condition, to
SDA crossing 70% of VDD
during the following START
condition.
1300
900 ns
ns
tLOW Clock LOW Time
Measured at the 30% of VDD
crossing.
1300
ns
tHIGH Clock HIGH Time
Measured at the 70% of VDD
crossing.
600
ns
tSU:STA START Condition Setup Time
tHD:STA START Condition Hold Time
tSU:DAT Input Data Setup Time
tHD:DAT Input Data Hold Time
tSU:STO STOP Condition Setup Time
tHD:STO STOP Condition Hold Time
tDH Output Data Hold Time
SCL rising edge to SDA falling
edge. Both crossing 70% of
VDD.
From SDA falling edge
crossing 30% of VDD to SCL
falling edge crossing 70% of
VDD.
From SDA exiting the 30% to
70% of VDD window, to SCL
rising edge crossing 30% of
VDD.
From SCL falling edge
crossing 30% of VDD to SDA
entering the 30% to 70% of
VDD window.
From SCL rising edge
crossing 70% of VDD, to SDA
rising edge crossing 30% of
VDD.
From SDA rising edge to SCL
falling edge. Both crossing
70% of VDD.
From SCL falling edge
crossing 30% of VDD, until
SDA enters the 30% to 70% of
VDD window.
600
600
100
0
600
600
0
ns
ns
ns
900 ns
ns
ns
ns
4 FN6451.0
March 30, 2007

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ISL12021 전자부품, 판매, 대치품
ISL12021
Serial Data (SDA)
SDA is a bi-directional pin used to transfer data into and out
of the device. It has an open drain output and may be ORed
with other open drain or open collector outputs. The input
buffer is always active (not gated) in normal mode.
An open drain output requires the use of a pull-up resistor.
The output circuitry controls the fall time of the output signal
with the use of a slope controlled pull-down. The circuit is
designed for 400kHz I2C interface speeds. It is disabled
when the backup power supply on the VBAT pin is activated.
VDD, GND
Chip power supply and ground pins. The device will operate
with a power supply from VDD = 2.7V to 5.5VDC. A 0.1µF
capacitor is recommended on the VDD pin to ground.
LVRSET (Low Voltage Reset)
Brown Out Reset Mode. The pin provides an interrupt signal
output. This signal notifies a host processor that the VDD
level has dropped below pre-programmed level, normally
85% of nominal VDD. The brownout trip level is
programmable via a control register. It is an open drain
active low output.
Functional Description
Power Control Operation
The power control circuit accepts a VDD and a VBAT input.
Many types of batteries can be used with Intersil RTC
products. For example, 3.0V or 3.6V Lithium batteries are
appropriate, and battery sizes are available that can power
the ISL1202x for up to 10 years. Another option is to use a
Super Capacitor for applications where VDD is interrupted
for up to a month. See the “Application Section” on page 21
for more information.
Normal Mode (VDD) to Battery Backup Mode
(VBAT)
To transition from the VDD to VBAT mode, both of the
following conditions must be met:
Condition 1:
VDD < VBAT - VBATHYS
where VBATHYS 50mV
Condition 2:
VDD < VTRIP
where VTRIP 2.2V
Battery Backup Mode (VBAT) to Normal Mode
(VDD)
The ISL12021 device will switch from the VBAT to VDD mode
when one of the following conditions occurs:
Condition 1:
VDD > VBAT + VBATHYS
where VBATHYS 50mV
Condition 2:
VDD > VTRIP + VTRIPHYS
where VTRIPHYS 30mV
These power control situations are illustrated in Figure 3 and
Figure 4.
VDD
VTRIP
VBAT
VBAT - VBATHYS
BATTERY BACKUP
MODE
2.2V
1.8V
VBAT + VBATHYS
FIGURE 3. BATTERY SWITCHOVER WHEN VBAT < VTRIP
VDD
VBAT
VTRIP
VTRIP
BATTERY BACKUP
MODE
3.0V
2.2V
VTRIP + VTRIPHYS
FIGURE 4. BATTERY SWITCHOVER WHEN VBAT > VTRIP
The I2C bus is deactivated in battery backup mode to reduce
power consumption. Aside from this, all RTC functions are
operational during battery backup mode. Except for SCL and
SDA, all the inputs and outputs of the ISL12021 are active
during battery backup mode unless disabled via the control
register.
The device Time Stamps the switchover from VDD to VBAT
and VBAT to VDD, and the time is stored in TSV2B and
TSB2V registers respectively. If multiple VDD power down
sequences occur before status is read, the earliest VDD to
VBAT power down time is stored and the most recent VBAT
to VDD time is stored.
Temperature conversion and compensation can be enabled
in battery backup mode. Bit BTSE in the BETA register
controls this operation as described in that register section.
Power Failure Detection
The ISL12021 provides a Real Time Clock Failure Bit
(RTCF) to detect total power failure. It allows users to
determine if the device has powered up after having lost all
power to the device (both VDD and VBAT).
7 FN6451.0
March 30, 2007

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