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PDF ISL12025 Data sheet ( Hoja de datos )
| Número de pieza | ISL12025 | |
| Descripción | Real-Time Clock/Calendar | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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®
Data Sheet
New Features
October 18, 2006
ISL12025
FN6371.1
Real-Time Clock/Calendar with EEPROM
The ISL12025 device is a low power real-time clock with
timing and crystal compensation, clock/calender, 64-bit
unique ID, power-fail indicator, two periodic or polled alarms,
intelligent battery backup switching, CPU Supervisor and
integrated 512 x 8-bit EEPROM, in a 16 Bytes per page
format.
The oscillator uses an external, low-cost 32.768kHz crystal.
The real-time clock tracks time with separate registers for
hours, minutes, and seconds. The device has calendar
registers for date, month, year and day of the week. The
calendar is accurate through 2099, with automatic leap year
correction.
Ordering Information
PART
TEMP.
PKG.
NUMBER PART VRESET RANGE PACKAGE DWG.
(Note) MARKING VOLTAGE (°C) (Pb-Free) #
ISL12025IBZ 12025IBZ 2.63V -40 to +85 8 Ld SOIC M8.15
ISL12025IVZ 2025IVZ
2.63V -40 to +85 8 Ld TSSOP M8.173
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
www.DataSheet4U.cotmin plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Add “-T” suffix for tape and reel.
Pinouts
X1
X2
RESET
GND
ISL12025
(8 LD SOIC)
TOP VIEW
18
27
36
45
VDD
VBAT
SCL
SDA
VBAT
VDD
X1
X2
ISL12025
(8 LD TSSOP)
TOP VIEW
18
27
36
45
SCL
SDA
GND
RESET
Features
• Real-Time Clock/Calendar
- Tracks Time in Hours, Minutes, and Seconds
- Day of the Week, Day, Month, and Year
• 64-bit Unique ID
• Two Non-Volatile Alarms
- Settable on the Second, Minute, Hour, Day of the Week,
Day, or Month
- Repeat Mode (periodic interrupts)
• Automatic Backup to Battery or SuperCap
• On-Chip Oscillator Compensation
- Internal Feedback Resistor and Compensation
Capacitors
- 64 Position Digitally Controlled Trim Capacitor
- 6 Digital Frequency Adjustment Settings to ±30ppm
• 512 x 8 Bits of EEPROM
- 16-Bytes Page Write Mode (32 total pages)
- 8 Modes of Block Lock™ Protection
- Single Byte Write Capability
• High Reliability
- Data Retention: 50 years
- Endurance: 2,000,000 Cycles Per Byte
• I2C* Interface
- 400kHz Data Transfer Rate
• 800nA Battery Supply Current
• Package Options
- 8 Ld SOIC and 8 Ld TSSOP Packages
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Utility Meters
• Audio/Video Components
• Modems
• Network Routers, Hubs, Switches, Bridges
• Cellular Infrastructure Equipment
• Fixed Broadband Wireless Equipment
• Pagers/PDA
• POS Equipment
• Test Meters/Fixtures
• Office Automation (Copiers, Fax)
• Home Appliances
• Computer Products
• Other Industrial/Medical/Automotive
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
*I2C is a Trademark of Philips. Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL12025
Serial Interface (I2C) Specifications (Continued)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
tLOW Clock LOW Time
Measured at the 30% of VDD
crossing.
1300
ns
tHIGH Clock HIGH Time
Measured at the 70% of VDD
crossing.
600
ns
tSU:STA START Condition Setup Time
tHD:STA START Condition Hold Time
tSU:DAT Input Data Setup Time
tHD:DAT Input Data Hold Time
tSU:STO STOP Condition Setup Time
tHD:STO STOP Condition Hold Time for
Read, or Volatile Only Write
tDH Output Data Hold Time
tR SDA and SCL Rise Time
SCL rising edge to SDA falling
edge. Both crossing 70% of VDD.
From SDA falling edge crossing
30% of VDD to SCL falling edge
crossing 70% of VDD.
From SDA exiting the 30% to 70%
of VDD window, to SCL rising edge
crossing 30% of VDD.
From SCL falling edge crossing
70% of VDD to SDA entering the
30% to 70% of VDD window.
From SCL rising edge crossing
70% of VDD, to SDA rising edge
crossing 30% of VDD.
From SDA rising edge to SCL
falling edge. Both crossing 70% of
VDD.
From SCL falling edge crossing
30% of VDD, until SDA enters the
30% to 70% of VDD window.
From 30% to 70% of VDD
600
600
100
0
600
600
0
20 +
0.1 x Cb
ns
ns
ns
ns
ns
ns
ns
250 ns
tF SDA and SCL Fall Time
From 70% to 30% of VDD
20 +
0.1 x Cb
250 ns
Cb Capacitive loading of SDA or SCL Total on-chip and off-chip
10
400 pF
Cpin SDA, and SCL Pin Capacitance
10 pF
tWC Non-Volatile Write Cycle Time
12 20 ms 10
NOTES:
3. RESET Inactive (no reset).
4. VIL = VDD x 0.1, VIH = VDD x 0.9, fSCL = 400kHz.
5. VRESET = 2.63V (VDD must be greater than VRESET), VBAT = 0V.
6. Bit BSW = 0 (Standard Mode), VBAT ≥1.8V.
7. Specified at +25°C.
8. In order to ensure proper timekeeping, the VDD SR- specification must be followed.
9. Parameter is not 100% tested.
10. tWC is the minimum cycle time to be allowed for any non-volatile Write by the user (it is the time from valid STOP condition at the end of Write
sequence of a serial interface Write operation) to the end of the self-timed internal non-volatile write cycle.
5 FN6371.1
October 18, 2006
5 Page 
ISL12025
TABLE 2. CLOCK/CONTROL MEMORY MAP
(Shaded cells indicate that NO other value is to be written to that bit. X indicates the bits are set according to the product variation
(see device ordering information). * indicates set at the factory, read-only)
BIT
REG
ADDR. TYPE NAME
7
6
5
4
3
2
1
0 RANGE
003F
0037
0036
0035
0034
0033
0032
0031
0030
0027
0026
0025
0024
0023
0022
0021
0020
0014
0013
0012
0011
0010
Status
RTC
(SRAM)
Device ID
Control
(EEPROM)
SR
Y2K
DW
YR
MO
DT
HR
MN
SC
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
PWR
DTR
ATR
INT
BL
BAT
0
0
Y23
0
0
MIL
0
0
ID77
ID67
ID57
ID47
ID37
ID27
ID17
ID07
SBIB
0
0
IM
BP2
AL1
0
0
Y22
0
0
0
M22
S22
ID76
ID66
ID56
ID46
ID36
ID26
ID16
ID06
BSW
0
0
AL1E
BP1
AL0
Y2K21
0
Y21
0
D21
H21
M21
S21
ID75
ID65
ID55
ID45
ID35
ID25
ID15
ID05
0
0
ATR5
AL0E
BP0
OSCF
Y2K20
0
Y20
G20
D20
H20
M20
S20
ID74
ID64
ID54
ID44
ID34
ID24
ID14
ID04
0
0
ATR4
0
WD1
0
Y2K13
0
Y13
G13
D13
H13
M13
S13
ID73
ID63
ID53
ID43
ID33
ID23
ID13
ID03
0
0
ATR3
0
WD0
RWEL
0
DY2
Y12
G12
D12
H12
M12
S12
ID72
ID62
ID52
ID42
ID32
ID22
ID12
ID02
VTS2
DTR2
ATR2
0
0
WEL
0
DY1
Y11
G11
D11
H11
M11
S11
ID71
ID61
ID51
ID41
ID31
ID21
ID11
ID01
VTS1
DTR1
ATR1
0
0
RTCF
Y2K10
DY0
Y10
G10
D10
H10
M10
S10
ID70
ID60
ID50
ID40
ID30
ID20
ID10
ID00
VTS0
DTR0
ATR0
0
0
19/20
0-6
0-99
1-12
1-31
0-23
0-59
0-59
01h
20h
00h
00h
00h
01h
00h
00h
00h
*
*
*
*
*
*
*
*
4Xh
00h
00h
00h
18h
000F
000E
000D
000C
000B
000A
0009
0008
0007
0006
0005
0004
0003
0002
0001
0000
Alarm1 Y2K1
(EEPROM) DWA1
YRA1
MOA1
DTA1
HRA1
MNA1
SCA1
Alarm0 Y2K0
(EEPROM) DWA0
YRA0
MOA0
DTA0
HRA0
MNA0
SCA0
0
EDW1
EMO1
EDT1
EHR1
EMN1
ESC1
0
EDW0
EMO0
EDT0
EHR0
EMN0
ESC0
0 A1Y2K21 A1Y2K20 A1Y2K13
0
0 A1Y2K10
0 0 0 0 DY2 DY1 DY0
Unused - Default = RTC Year value (No EEPROM) - Future expansion
0 0 A1G20 A1G13 A1G12 A1G11 A1G10
0 A1D21 A1D20 A1D13 A1D12 A1D11 A1D10
0 A1H21 A1H20 A1H13 A1H12 A1H11 A1H10
A1M22 A1M21 A1M20 A1M13 A1M12 A1M11 A1M10
A1S22 A1S21 A1S20 A1S13 A1S12 A1S11 A1S10
0 A0Y2K21 A0Y2K20 A0Y2K13
0
0 A0Y2K10
0 0 0 0 DY2 DY1 DY0
Unused - Default = RTC Year value (No EEPROM) - Future expansion
0 0 A0G20 A0G13 A0G12 A0G11 A0G10
0 A0D21 A0D20 A0D13 A0D12 A0D11 A0D10
0 A0H21 A0H20 A0H13 A0H12 A0H11 A0H10
A0M22 A0M21 A0M20 A0M13 A0M12 A0M11 A0M10
A0S22 A0S21 A0S20 A0S13 A0S12 A0S11 A0S10
19/20
0-6
1-12
1-31
0-23
0-59
0-59
19/20
0-6
1-12
1-31
0-23
0-59
0-59
20h
00h
00h
00h
00h
00h
00h
20h
00h
00h
00h
00h
00h
00h
11 FN6371.1
October 18, 2006
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet ISL12025.PDF ] | |
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