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PDF ISL54058 Data sheet ( Hoja de datos )

Número de pieza ISL54058
Descripción Dual 4 to 1 Analog Multiplexer
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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®
Data Sheet
September 29, 2006
ISL54058
FN6380.0
Ultra Low ON-Resistance, Low-Voltage,
Single Supply, Dual 4 to 1 Analog
Multiplexer
The Intersil ISL54058 device contains precision, bidirectional,
analog switches configured as a dual 4-channel
multiplexer/demultiplexer, designed to operate from a single
+1.6V to +3.6V supply.
ON resistance is 0.41with a +3V supply and 0.61with a
single +1.8V supply. Each switch can handle rail to rail
analog signals. The off-leakage current is only 4nA max at
+25°C or 40nA max at +85°C with a +3.3V supply.
All digital inputs are 1.8V logic-compatible when using a
single +3V supply.
The ISL54058 is a dual 4 to 1 multiplexer device that is
offered in a 16 Ld 2.6x1.8x0.5mm µTQFN package.
Table 1 summarizes the performance of this family.
TABLE 1. FEATURES AT A GLANCE
ISL54058
Configuration
Dual 4:1 Mux
3Vwww.DataSheet4U.com RON
3V tRANS
1.8V RON
1.8V tRANS
Packages
0.41
29ns
0.61
34ns
16 Ld 2.6x1.8x0.5mm µTQFN
Features
Pb-Free Plus Anneal Available (RoHS Compliant)
• ON Resistance (RON)
- V+ = +3.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.41
- V+ = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.61
• RON Matching Between Channels. . . . . . . . . . . . . . . . 0.09
• RON Flatness Across Signal Range . . . . . . . . . . . . . . 0.07
• Single Supply Operation. . . . . . . . . . . . . . . . . +1.6V to +3.6V
• Low Power Consumption (PD). . . . . . . . . . . . . . . . . <0.18µW
• Fast Switching Action (VS = +3V)
- tRANS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29ns
• Break-Before-Make
• High Current Handling Capacity (300mA Continuous)
• Available in 16 Ld 2.6x1.8x0.5mm µTQFN
• 1.8V CMOS-Logic Compatible (+3V Supply)
Applications
• Battery Powered, Handheld, and Portable Equipment
- Cellular/Mobile Phones
- Pagers
- Laptops, Notebooks, Palmtops
• Portable Test and Measurement
• Medical Equipment
• Audio and Video Switching
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Application Note AN557 “Recommended Test Procedures
for Analog Switches”
Ordering Information
PART NUMBER (NOTE) PART MARKING
ISL54058IRUZ-T
GAC
TEMP. RANGE (°C)
-40 to +85
PACKAGE
16 Ld Thin µQFN Tape and Reel (Pb-free)
PKG. DWG. #
L16.2.6x1.8A
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination
finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-
free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C.
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

1 page




ISL54058 pdf
Test Circuits and Waveforms
ISL54058
LOGIC
INPUT
V+
0V
50%
tTRANS
tr < 5ns
tf < 5ns
VA0, VB0
VOUT
90%
SWITCH
OUTPUT
0V 10%
0V
tTRANS
Logic input waveform is inverted for switches that have the opposite
logic sense.
C
V+
LOGIC
INPUT
V+
C
A0,B0
A1-A3
B1-B3
ADD1-0 GND
COMA
COMB
VOUT
RL
50
CL
35pF
Repeat test for other switches. CL includes fixture and stray
capacitance.
VOUT
=
V(NO or NC)
------------R-----L-------------
RL + R(ON)
FIGURE 1A. ADDRESS tTRANS MEASUREMENT POINTS
FIGURE 1B. ADDRESS tTRANS TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
LOGIC
INPUT
V+
0V
SWITCH
OUTPUT
VOUT
0V
tr < 5ns
tf < 5ns
tBBM
90%
C
V+
LOGIC
INPUT
V+
C
A0-A3
B0-B3
ADD1-0
COMA
COMB
VOUT
RL
50
CL
35pF
GND
FIGURE 2A. tBBM MEASUREMENT POINTS
Repeat test for other switches. CL includes fixture and stray
capacitance.
FIGURE 2B. tBBM TEST CIRCUIT
FIGURE 2. BREAK-BEFORE-MAKE TIME
5 FN6380.0
September 29, 2006

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