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EL5126 데이터시트 PDF




Intersil Corporation에서 제조한 전자 부품 EL5126은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 EL5126 자료 제공

부품번호 EL5126 기능
기능 8-Channel TFT-LCD Reference Voltage Generator
제조업체 Intersil Corporation
로고 Intersil Corporation 로고


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EL5126 데이터시트, 핀배열, 회로
®
Data Sheet
August 24, 2006
EL5126
FN7337.2
8-Channel TFT-LCD Reference Voltage
Generator
The EL5126 is designed to produce
the reference voltages required in
TFT-LCD applications. Each output is
programmed to the required voltage with 10 bits of
resolution. Reference pins determine the high and low
voltages of the output range, which are capable of swinging
to either supply rail. Programming of each output is
performed using the serial interface.
A number of the EL5126 can be stacked for applications
requiring more than 8 outputs. The reference inputs can be
tied to the rails, enabling each part to output the full voltage
range, or alternatively, they can be connected to external
resistors to split the output range and enable finer
resolutions of the outputs.
The EL5126 has 8 outputs and is available in a 32 Ld QFN
package. It is specified for operation over the full -40°C to
+85°C temperature range.
Ordering Information
PART
NUMBER
TAPE
PART
AND
MARKING PACKAGE REEL
PKG. NO.
EL5126CL
5126CL 32 Ld QFN - MDP0046
EL5126CLZ
(Note)
5126CLZ 32 Ld QFN
(Pb-free)
- MDP0046
EL5126CL-T7 5126CL 32 Ld QFN 7” MDP0046
EL5126CLZ-T7 5126CLZ 32 Ld QFN
(Note)
(Pb-free)
7” MDP0046
EL5126CL-T13 5126CL 32 Ld QFN 13” MDP0046
EL5126CLZ-T13 5126CLZ 32 Ld QFN 13” MDP0046
(Note)
(Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
Features
• 8-channel reference outputs
• Accuracy of ±0.1%
• Supply voltage of 4.5V to 16.5V
• Digital supply 3.3V to 5V
• Low supply current of 10mA
• Rail-to-rail capability
• I2C control interface
Applications
• TFT-LCD drive circuits
• Reference voltage generators
Pinout
EL5126
(32 LD 5X6 QFN)
TOP VIEW
VS 1
VSD 2
VS 3
REFH 4
REFL 5
AGND 6
CAP 7
NC 8
VS 9
THERMAL
PAD
25 OUTA
24 OUTB
23 OUTC
22 OUTD
21 DGND
20 OUTE
19 OUTF
18 OUTG
17 OUTH
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc.
All other trademarks mentioned are the property of their respective owners.




EL5126 pdf, 반도체, 판매, 대치품
Typical Performance Curves (Continued)
EL5126
1.2
VS=VREFH=15V
1.0 VREFL=0V
0.8
0.6
0.4
0.2
0
3 3.2 3.4 3.5 3.8 4 4.2 4.4 4.5 4.8 5
VSD (V)
FIGURE 3. DIGITAL SUPPLY VOLTAGE vs DIGITAL SUPPLY
CURRENT
VS=VREFH=15V
M=400ns/DIV
5mA
0mA
CL=1nF
RS=20Ω
CL=4.7nF
RS=20Ω
CL=180pF
VS=VREFH=15V
M=400ns/DIV
0mA
5mA
5V
CL=1nF
RS=20Ω
CL=180pF
5mA/DIV
CL=4.7nF
RS=20Ω
200mV/DIV
FIGURE 4. TRANSIENT LOAD REGULATION (SOURCING)
5V
0V
5V
0V
10V
5V
0V OUTPUT
SCLK
SDA
M=400µs/DIV
FIGURE 5. TRANSIENT LOAD REGULATION (SINKING)
FIGURE 6. LARGE SIGNAL RESPONSE (RISING FROM 0V
TO 8V)
SCLK
SDA
OUTPUT
M=400µs/DIV
FIGURE 7. LARGE SIGNAL RESPONSE (FALLING FROM 8V
TO 0V)
5V
0V
5V
0V
200mV
0V
SCLK
SDA
OUTPUT
M=400µs/DIV
FIGURE 8. SMALL SIGNAL RESPONSE (RISING FROM 0V
TO 200mV)
4

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EL5126 전자부품, 판매, 대치품
I2C Timing Diagram 1
STANDARD MODE (STD/REG = HIGH) WRITE MODE
= don’t care
I2C Start
Device Address W A
Data 1
A
Data 2
A
Data 3
Data
I2C
Data In
A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5
I2C
CLK In
12345678 12345678 12345678
Data 16
A
D2 D1 D0
678
Stop
STANDARD MODE (STD/REG = HIGH) READ MODE
I2C
Data
Start
Device Address R A
Data 1 A Data 2
A Data 3
I2C
Data In
A6 A5 A4 A3 A2 A1 A0
I2C
Data Out
D7 D6 D5 D4 D3 D2 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5
I2C
CLK In
12345678 12345678 12345678
Data 16
NA Stop
D2 D1 D0
678
REGISTER MODE (STD/REG = LOW) WRITE MODE
I2C
Data
I2C
Data In
Start
Device Address W A Register Address A
Data 1
A
Data 2
A
A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 R3 R2 R1 R0 D7 D6 D5 D4 D3 D2 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
I2C
CLK In
12345678 12345678 12345678 12345678
Stop
REGISTER MODE (STD/REG = LOW) READ MODE
I2C Start
Device Address W A Register Address A Start Device Address R A
Data 1
A
Data 2
NA Stop
Data
I2C
Data In
A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 R3 R2 R1 R0
A6 A5 A4 A3 A2 A1 A0
I2C
Data Out
D7 D6 D5 D4 D3 D2 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
I2C
CLK In
12345678 12345678
12345678 12345678 12345678

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