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EL5325 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 EL5325
기능 12-Channel TFT-LCD Reference Voltage Generator
제조업체 Intersil Corporation
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EL5325 데이터시트, 핀배열, 회로
®
Data Sheet
March 5, 2004
EL5325
FN7437.1
12-Channel TFT-LCD Reference Voltage
Generator
The EL5325 is designed to produce
the reference voltages required in
TFT-LCD applications. Each output is
programmed to the required voltage with 10 bits of
resolution. Reference pins determine the high and low
voltages of the output range, which are capable of swinging
to either supply rail. Programming of each output is
performed using the 3-wire, SPI compatible interface.
A number of EL5325 can be stacked for applications
requiring more than 12 outputs. The reference inputs can be
tied to the rails, enabling each part to output the full voltage
range, or alternatively, they can be connected to external
resistors to split the output range and enable finer
resolutions of the outputs.
The EL5325 has 12 outputs and is available in a 28-pin
TSSOP package. They are specified for operation over the
full -40°C to +85°C temperature range.
Ordering Information
www.DataSheet4U.com
PART
NUMBER
PACKAGE
TAPE &
REEL
PKG.
DWG. #
EL5325IRZ
(Note)
28-Pin TSSOP
(Pb-Free)
-
MDP0044
EL5325IRZ-T7
(Note)
28-Pin TSSOP
(Pb-Free)
7”
MDP0044
EL5325IRZ-T13
(Note)
28-Pin TSSOP
(Pb-Free)
13”
MDP0044
NOTE: Intersil Pb-Free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and Pb-
free soldering operations. Intersil Pb-Free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J Std-020B.
Features
• 12-channel reference outputs
• Accuracy of ±1%
• Supply voltage of 5V to 16.5V
• Digital supply 3.3V to 5V
• Low supply current of 10mA
• Rail-to-rail capability
• Internal thermal protection
• Pb-Free Available
Applications
• TFT-LCD drive circuits
• Reference voltage generators
Pinout
EL5325
(28-PIN TSSOP)
TOP VIEW
ENA 1
SDI 2
SCLK 3
SDO 4
EXT_OSC 5
VS 6
NC 7
VSD 8
REFH 9
REFL 10
VS 11
GND 12
CAP 13
NC 14
28 OUTA
27 OUTB
26 OUTC
25 GND
24 OUTD
23 OUTE
22 OUTF
21 OUTG
20 OUTH
19 OUTI
18 GND
17 OUTJ
16 OUTK
15 OUTL
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc.
All other trademarks mentioned are the property of their respective owners.




EL5325 pdf, 반도체, 판매, 대치품
EL5325
Typical Performance Curves
VS=15V, VSD=5V, VREFH=13V, VREFL=2V
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
10
210 410 610 810 1010
INPUT CODE
FIGURE 1. DIFFERENTIAL NONLINEARITY vs CODE
REFH=13V, REFL=2V
1.5
1
0.5
0
-0.5
-1
0 200 400 600 800 1000 1200
CODE
FIGURE 2. INTEGRAL NONLINEARITY ERROR
VS=VREFH=15V
M=400ns/DIV
0mA
5mA
5V
CL=1nF
RS=20
CL=180pF
5mA/DIV
CL=4.7nF
RS=20
200mV/DIV
FIGURE 3. TRANSIENT LOAD REGULATION (SOURCING)
VS=VREFH=15V
M=400ns/DIV
5mA
0mA
CL=1nF
RS=20
CL=4.7nF
RS=20
CL=180pF
FIGURE 4. TRANSIENT LOAD REGULATION (SINKING)
M=400µs/DIV
5V
0V
5V
0V
10V
5V
0V OUTPUT
SCLK
SDA
FIGURE 5. LARGE SIGNAL RESPONSE (RISING FROM 0V
TO 8V)
4
M=400µs/DIV
SCLK
SDA
OUTPUT
FIGURE 6. LARGE SIGNAL RESPONSE (FALLING FROM 8V
TO 0V)

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EL5325 전자부품, 판매, 대치품
EL5325
PARAMETER
T
tr/tf
tHE
tSE
tHD
tSD
tW
TABLE 2. SERIAL TIMING PARAMETERS
RECOMMENDED OPERATING RANGE
DESCRIPTION
200ns
Clock Period
0.05 * T
Clock Rise/Fall Time
10ns
ENA Hold Time
10ns
ENA Setup Time
10ns
Data Hold Time
10ns
Data Setup Time
0.50 * T
Clock Pulse Width
CONTROL CHANNEL ADDRESS
C1 C0 A3 A2 A1 A0 D9
0 0 00000
0 0 00001
0 0 00001
0 0 00111
0 0 01110
0 1 01110
TABLE 3. SERIAL PROGRAMMING EXAMPLES
DATA
D8 D7 D6 D5 D4 D3 D2 D1 D0
CONDITION
0 0 0 0 0 0 0 0 0 Internal Oscillator, Channel A, Value = 0
1 1 1 1 1 1 1 1 1 Internal Oscillator, Channel A, Value = 1023
0 0 0 0 0 0 0 0 0 Internal Oscillator, Channel A, Value = 512
0 0 0 0 0 0 0 0 1‘t Internal Oscillator, Channel C, Value = 513
0 0 0 0 1 1 1 1 1 Internal Oscillator, Channel H, Value = 31
0 0 0 0 1 1 1 1 1 External Oscillator, Channel H, Value = 31
Analog Section
TRANSFER FUNCTION
The transfer function is:
VOUT(IDEAL )
=
VREFL
+
-d---a----t--a--
1024
×
(VREFH
-
VREFL)
where data is the decimal value of the 10-bit data binary
input code.
The output voltages from the EL5325 will be derived from
the reference voltages present at the VREFL and VREFH
pins. The impedance between those two pins is about 32k.
Care should be taken that the system design holds these two
reference voltages within the limits of the power rails of the
EL5325. GND < VREFH VS and GND VREFL VREFH.
In some LCD applications that require more than 12
channels, the system can be designed such that one
EL5325 will provide the Gamma correction voltages that are
more positive than the VCOM potential. The second EL5325
can provide the Gamma correction voltage more negative
than the VCOM potential. The Application Drawing shows a
system connected in this way.
CLOCK OSCILLATOR
The EL5325 requires an internal clock or external clock to
refresh its outputs. The outputs are refreshed at the falling OSC
clock edges. The output refreshed switches open at the rising
edges of the OSC clock. The driving load shouldn’t be changed
at the rising edges of the OSC clock. Otherwise, it will generate
a voltage error at the outputs. This clock may be input or output
via the clock pin labeled OSC. The internal clock is provided by
an internal oscillator running at approximately 21kHz and can
be output to the OSC pin. In a 2 chip system, if the driving loads
are stable, one chip may be programmed to use the internal
oscillator; then the OSC pin will output the clock from the
internal oscillator. The second chip may have the OSC pin
connected to this clock source.
For transient load application, the external clock Mode
should be used to ensure all functions are synchronized
together. The positive edge of the external clock to the OSC
pin should be timed to avoid the transient load effect. The
Application Drawing shows the LCD H rate signal used, here
the positive clock edge is timed to avoid the transient load of
the column driver circuits.
After power on, the chip will start with the internal oscillator
mode. At this time, the OSC pin will be in a high impedance
condition to prevent contention. By setting B14 to high, the
chip is on external clock mode. Setting B14 to low, the chip is
on internal clock mode.
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