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EL7532 데이터시트 PDF




Intersil Corporation에서 제조한 전자 부품 EL7532은 전자 산업 및 응용 분야에서
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부품번호 EL7532 기능
기능 Monolithic 2A Step-Down Regulator
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EL7532 데이터시트, 핀배열, 회로
®
Data Sheet
December 8, 2006
EL7532
FN7435.7
Monolithic 2A Step-Down Regulator
The EL7532 is a synchronous, integrated FET 2A step-down
regulator with internal compensation. It operates with an
input voltage range from 2.5V to 5.5V, which accommodates
supplies of 3.3V, 5V, or a single Li-Ion battery source. The
output can be externally set from 0.8V to VIN with a resistive
divider.
The EL7532 features PWM mode control. The operating
frequency is typically 1.5MHz. Additional features include a
100ms Power-On-Reset output, <1µA shut-down current,
short-circuit protection, and over-temperature protection.
The EL7532 is available in the 10-pin MSOP package,
making the entire converter occupy less than 0.18 in2 of
PCB area with components on one side only. The package is
specified for operation over the full -40°C to +85°C
temperature range.
Ordering Information
PART TAPE &
PKG.
PART NUMBER MARKING REEL PACKAGE DWG. #
EL7532IY
www.DataSheet4U.comEL7532IY-T7
BABAA
BABAA
- 10 Ld MSOP MDP0043
7” 10 Ld MSOP MDP0043
EL7532IY-T13 BABAA
13” 10 Ld MSOP MDP0043
EL7532IYZ
(Note)
BAARA
- 10 Ld MSOP MDP0043
(Pb-free)
EL7532IYZ-T7 BAARA
(Note)
7” 10 Ld MSOP MDP0043
(Pb-free)
EL7532IYZ-T13 BAARA
(Note)
13” 10 Ld MSOP MDP0043
(Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
Pinout
EL7532 (10 LD MSOP)
TOP VIEW
1 SGND
2 PGND
3 LX
4 VIN
5 VDD
FB 10
VO 9
POR 8
EN 7
RSI 6
Features
• 2A continuous current (from -40°C to +85°C)
• Less than 0.18 in2 footprint for the complete 2A converter
• Max height 1.1mm MSOP10
• 1.5MHz (typ.) switching frequency
• 100ms Power-On-Reset output (POR)
• Internally-compensated voltage mode controller
• Up to 94% efficiency
• <1µA shut-down current
• Overcurrent and over temperature protection
• Pb-free plus anneal available (RoHS compliant)
Applications
• PDA and pocket PC computers
• Bar code readers
• ADSL modems
• Portable instruments
• Li-Ion battery powered devices
• ASIC/FPGA/DSP supplies
• Set top boxes
Typical Application Schematic
VS (2.5V to 5.5V)
L1
R3 100Ω
C2 C3
VIN
VDD
LX 1.8µH
C1
10µF
10µF
0.1µF
EL7532
VO
R5 100kΩ
R4 100kΩ
R6
100kΩ
POR
EN
RSI
PGND
SGND
R1*
124kΩ
FB
R2*
100kΩ
C4
470pF
VO (1.8V @ 2A)
* VO = 0.8V * (1 + R1 / R2)
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004, 2005, 2006. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.




EL7532 pdf, 반도체, 판매, 대치품
Typical Performance Curves
EL7532
100
80
60 VO = 1.2V
VO = 3.3V
40
VO = 1.8V
20
MAXIMUM EFFICIENCY, η = 95%
0
0 0.5 1 1.5
2
2.5
IOUT (A)
FIGURE 1. EFFICIENCY vs IOUT @ VIN = 5V
100
80
60
VO = 1.2V
40
20
VO = 2.5V
VO = 1.8V
MAXIMUM EFFICIENCY, η = 95%
0
0 0.5 1 1.5
2
2.5
IOUT (A)
FIGURE 2. EFFICIENCY vs IOUT @ VIN = 3.3V
100
80
60
VO = 1.8V
40 VO = 1.2V
20
MAXIMUM EFFICIENCY, η = 94%
0
0 0.5 1 1.5
2
2.5
IOUT (A)
FIGURE 3. EFFICIENCY vs IOUT @ VIN = 2.5V
1
0.6 VO = 0.8V
IO = 2A
0.2
-0.2 VO = 2.5V
-0.6
VO = 3.3V
-1
2.5 3 3.5 4 4.5 5 5.5
VIN (V)
FIGURE 4. LINE REGULATION
6
1
0.6
0.2 VO = 0.8V
VO = 3.3V
-0.2
-0.6
-1
0 0.5 1 1.5 2 2.5
IOUT (A)
FIGURE 5. LOAD REGULATION @ VIN = 5V
4
1
0.6
0.2 VO = 0.8V
-0.2 VO = 2.5V
-0.6
-1
0 0.5 1 1.5 2 2.5
IOUT (A)
FIGURE 6. LOAD REGULATION @ VIN = 3.3V
FN7435.7
December 8, 2006

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EL7532 전자부품, 판매, 대치품
EL7532
At extreme conditions (VIN < 3V, IO > 0.7A, and junction
temperature higher than 75°C), input cap C1 is
recommended to be 22µF. Otherwise, if any of the above 3
conditions is not true, C1 can remain as low as 10µF.
The RMS current present at the input capacitor is decided by
the following formula:
IINRMS
=
-----V----O------×----(---V----I--N-----------V----O-----)
VIN
×
IO
This is about half of the output current IO for all the VO. This
input capacitor must be able to handle this current.
The inductor peak-to-peak ripple current is given as:
ΔIIL = -(--V----IL--N---×------V---V-I--N-O----×-)---×-f--S--V----O---
• L is the inductance
• fS the switching frequency (nominally 1.5MHz)
The inductor must be able to handle IO for the RMS load
current, and to assure that the inductor is reliable, it must
handle the 3A surge current that can occur during a current
limit condition.
In addition to decoupling capacitors and inductor value, it is
important to properly size the phase-lead capacitor C4
(Refer to the Typical Application Diagram). The phase-lead
capacitor creates additional phase margin in the control loop
by generating a zero and a pole in the transfer function. As a
general rule of thumb, C4 should be sized to start the phase-
lead at a frequency of ~2.5kHz. The zero will always appear
at lower frequency than the pole and follow the equation
below:
fZ
=
----------1------------
2πR2C4
Over a normal range of R2 (~10-100k), C4 will range from
~470-4700pF. The pole frequency cannot be set once the
zero frequency is chosen as it is dictated by the ratio of R1
and R2, which is solely determined by the desired output set
point. The equation below shows the pole frequency
relationship:
fP
=
-------------------1--------------------
2π(R1 R2)C4
Current Limit and Short-Circuit Protection
The current limit is set at about 3A for the PMOS. When a
short-circuit occurs in the load, the preset current limit
restricts the amount of current available to the output, which
causes the output voltage to drop below the preset voltage.
In the meantime, the excessive current heats up the
regulator until it reaches the thermal shut-down point.
Thermal Shut-Down
Once the junction reaches about 145°C, the regulator shuts
down. Both the P channel and the N channel MOSFETs turn
off. The output voltage will drop to zero. With the output
MOSFETs turned off, the regulator will soon cool down.
Once the junction temperature drops to about 130°C, the
regulator will restart again in the same manner as the EN pin
connects to logic HI.
Thermal Performance
The EL7532 is in a fused-lead MSOP10 package. Compared
to the regular MSOP10 package, the fused-lead package
provides lower thermal resistance. The typical θJA of
115°C/W (See Thermal Information section in spec table)
can be improved by maximizing the copper area around the
pins. A θJA of 100°C/W can be achieved on a 4-layer board
and 125°C/W on a 2-layer board. Refer to Intersil’s Tech
Brief, TB379, for more information on thermal resistance.
Layout Considerations
The layout is very important for the converter to function
properly. The following PC layout guidelines should be
followed:
• Separate the Power Ground ( ) and Signal Ground ( );
connect them only at one point right at the pins
• Place the input capacitor as close to VIN and PGND pins
as possible
• Make the following PC traces as small as possible:
- from LX pin to L
- from CO to PGND
• If used, connect the trace from the FB pin to R1 and R2 as
close as possible
• Maximize the copper area around the PGND pin
• Place several via holes under the chip to additional ground
plane to improve heat dissipation
The demo board is a good example of layout based on this
outline. Please refer to the EL7532 Application Brief.
7 FN7435.7
December 8, 2006

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