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PDF EL9115 Data sheet ( Hoja de datos )
| Número de pieza | EL9115 | |
| Descripción | Triple Analog Video Delay Line | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de EL9115 (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
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®
Data Sheet
September 8, 2005
EL9115
FN7441.2
Triple Analog Video Delay Line
The EL9115 is a triple analog delay line that allows skew
compensation between any three signals. This part is perfect
for compensating for the skew introduced by a typical CAT-5
cable with differing electrical lengths on each pair.
The EL9115 can be programmed in steps of 2ns up to 62ns
total delay on each channel.
Ordering Information
PART NUMBER PACKAGE
TAPE &
REEL
PKG. DWG. #
EL9115IL
20-Pin QFN
(5mm x 5mm)
-
MDP0046
EL9115IL-T7
20-Pin QFN
(5mm x 5mm)
7”
MDP0046
EL9115IL-T13
20-Pin QFN
(5mm x 5mm)
13”
MDP0046
EL9115ILZ
(See Note)
20-Pin QFN
(5mm x 5mm)
(Pb-Free)
-
MDP0046
EL9115ILZ-T7
www.DataSheet4U.com(See Note)
20-Pin QFN
(5mm x 5mm)
(Pb-Free)
7”
MDP0046
EL9115ILZ-T13
(See Note)
20-Pin QFN
(5mm x 5mm)
(Pb-Free)
13”
MDP0046
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
Features
• 62ns total delay
• 2ns delay step increments
• Operates from ±5V supply
• Up to 122MHz bandwidth
• Low power consumption
• 20-pin QFN (5mm x 5mm) package
• Pb-Free plus anneal available (RoHS compliant)
Applications
• Skew control for RGB
• Analog beamforming
Pinout
EL9115
[20-PIN QFN (5MM X 5MM)]
TOP VIEW
VSP 1
RIN 2
GND 3
GIN 4
VSM 5
THERMAL
PAD
15 ROUT
14 GNDO
13 GOUT
12 VSMO
11 BOUT
EXPOSED DIEPLATE SHOULD BE CONNECTED TO -5V
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2004, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
Typical Performance Curves
Vout = 1Vptp
EL9115
3 Channels
FIGURE 7. DISTORTION vs FREQUENCY
X2 Hi_62ns Delay
X2 Hi_0ns Delay
X2 Low_62ns Delay
X2 Low_0ns Delay
FIGURE 9. ISUPPLY+ vs VSUPPLY+
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
1.2 CONDUCTIVITY TEST BOARD
1
833mW
0.8
0.6
0.4
θJA =1Q5F0°NC2/0W
0.2
0
0 25 50 75 85 100 125 150
AMBIENT TEMPERATURE (°C)
FIGURE 11. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
DELAY TIME (ns)
FIGURE 8. POSITVE SUPPLY CURRENT vs DELAY TIME
X2 Hi_62ns Delay
X2 Hi_0ns Delay
X2 Low_62ns Delay
X2 Low_0ns Delay
FIGURE 10. ISUPPLY- vs VSUPPLY-
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD - QFN EXPOSED
DIEPAD SOLDERED TO PCB PER JESD51-5
4.5
4
3.5 3.125W
3
2.5
2
1.5
θJA =4Q0F°NC2/W0
1
0.5
0
0 25 50 75 85 100 125 150
AMBIENT TEMPERATURE (°C)
FIGURE 12. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
5 FN7441.2
September 8, 2005
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet EL9115.PDF ] | |
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