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X4005 데이터시트 PDF




Intersil Corporation에서 제조한 전자 부품 X4005은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 X4005 기능
기능 (X4003 / X4005) CPU Supervisor
제조업체 Intersil Corporation
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X4005 데이터시트, 핀배열, 회로
®
Data Sheet
X4003, X4005
May 11, 2006
FN8113.1
CPU Supervisor
FEATURES
• Selectable watchdog timer
—Select 200ms, 600ms, 1.4s, off
• Low VCC detection and reset assertion
—Five standard reset threshold voltages
nominal 4.62V, 4.38V, 2.92V, 2.68V, 1.75V
—Adjust low VCC reset threshold voltage using
special programming sequence
—Reset signal valid to VCC = 1V
• Low power CMOS
—12µA typical standby current, watchdog on
—800nA typical standby current watchdog off
—3mA active current
• 400kHz I2C interface
• 1.8V to 5.5V power supply operation
• Available packages
—8 Ld SOIC
—8 Ld MSOP
• Pb-free plus anneal available (RoHS compliant)
www.DataSheet4U.com
BLOCK DIAGRAM
WP
SDA
SCL
VCC
Watchdog Transition
Detector
Data
Register
Command
Decode &
Control
Logic
VCC Threshold
Reset logic
Control
Register
VTRIP
+
-
DESCRIPTION
These devices combine three popular functions,
Power-on Reset Control, Watchdog Timer, and Supply
Voltage Supervision. This combination lowers system
cost, reduces board space requirements, and
increases reliability.
Applying power to the device activates the power-on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
The Watchdog Timer provides an independent
protection mechanism for microcontrollers. When the
microcontroller fails to restart a timer within a select-
able time out interval, the device activates the
RESET/RESET signal. The user selects the interval
from three preset values. Once selected, the interval
does not change, even after cycling the power.
The device’s low VCC detection circuitry protects the
user’s system from low voltage conditions, resetting the
system when VCC falls below the minimum VCC trip
point. RESET/RESET is asserted until VCC returns to
proper operating level and stabilizes. Five industry stan-
dard VTRIP thresholds are available; however, Intersil’s
unique circuits allow the threshold to be reprogrammed
to meet custom requirements, or to fine-tune the thresh-
old for applications requiring higher precision.
Watchdog
Timer Reset
Reset &
Watchdog
Timebase
Power-on and
Low Voltage
Reset
Generation
RESET (X4003)
RESET (X4005)
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.




X4005 pdf, 반도체, 판매, 대치품
PIN CONFIGURATION
8-Pin JEDEC SOIC, MSOP
NC
NC
RESET
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
X4003, X4005
PIN DESCRIPTION
Pin
(SOIC/DIP)
1
2
3
Pin
TSSOP
3
4
5
46
57
68
71
82
Pin
(MSOP)
2
3
4
5
6
1
Name
NC
NC
RESET/
RESET
VSS
SDA
SCL
WP
VCC
Function
No internal connections
No internal connections
Reset Output. RESET/RESET is an active LOW/HIGH, open
drain output which goes active whenever VCC falls below the min-
imum VCC sense level. It will remain active until VCC rises above
the minimum VCC sense level for 250ms. RESET/
RESET goes active if the watchdog timer is enabled and SDA re-
mains either HIGH or LOW longer than the selectable Watchdog
time out period. A falling edge of SDA, while SCL also toggles from
HIGH to LOW followed by a stop condition
resets the watchdog timer. RESET/RESET goes active on power-
up and remains active for 250ms after the power supply stabilizes.
Ground
Serial Data. SDA is a bidirectional pin used to transfer data into
and out of the device. It has an open drain output and may be wire
ORed with other open drain or open collector outputs. This pin re-
quires a pull up resistor and the input buffer is
always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA while
SCL also toggles from HIGH to LOW follow by a stop condition re-
sets the watchdog timer. The absence of this procedure within the
watchdog time out period results in RESET/RESET going active.
Serial Clock. The serial clock controls the serial bus timing for
data input and output.
Write Protect. WP HIGH prevents changes to the watchdog
timer setting.
Supply voltage
4 FN8113.1
May 11, 2006

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X4005 전자부품, 판매, 대치품
X4003, X4005
Figure 4. VTRIP Programming Sequence
VTRIP Programming
Execute
RSeesqeut eVnTcReIP
Set VCC = VCC Applied =
Desired VTRIP
New VCC Applied =
Old VCC Applied - Error
Execute
RSeesqeut eVnTcReIP
Execute
Set VTRIP
Sequence
Apply 5V to VCC
Decrement VCC
(VCC = VCC - 50mV)
New VCC Applied =
Old VCC applied + Error
RESET pin
goes active?
YES
Error Emax
Measured
Desired
VVTTRRIIPP
-
-Emax < Error < Emax
DONE
NO
Error –Emax
Emax = Maximum Allowable VTRIP Error
Control Register
The control register provides the user a mechanism
for changing the watchdog timer settings. watchdog
timer bits are nonvolatile and do not change when
power is removed.
The control register is accessed with a special preamble
in the slave byte (1011) and is located at address 1FFh.
It can only be modified by performing a control register
write operation. Only one data byte is allowed for each
register write operation. Prior to writing to the control reg-
ister, the WEL and RWEL bits must be set using a two
step process, with the whole sequence requiring 3 steps.
See "Writing to the Control Register" below.
The user must issue a stop after sending the control
byte to the register to initiate the nonvolatile cycle that
stores WD1 and WD0. The X4003/X4005 will not
acknowledge any data bytes written after the first byte
is entered.
The state of the control register can be read at any
time by performing a serial read operation. Only one
byte is read by each register read operation. The
X4003/X4005 resets itself after the first byte is read.
The master should supply a stop condition to be con-
sistent with the bus protocol, but a stop is not required
to end this operation.
76 5 4
0 WD1 WD0 0
3 2 10
0 RWEL WEL 0
7 FN8113.1
May 11, 2006

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