Datasheet.kr   

X4043 데이터시트 PDF




Intersil Corporation에서 제조한 전자 부품 X4043은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 X4043 자료 제공

부품번호 X4043 기능
기능 (X4043 / X4045) CPU Supervisor
제조업체 Intersil Corporation
로고 Intersil Corporation 로고


X4043 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




전체 24 페이지수

미리보기를 사용할 수 없습니다

X4043 데이터시트, 핀배열, 회로
®
Data Sheet
September 30, 2005
X4043, X4045
4k, 512 x 8 Bit
FN8118.1
CPU Supervisor with 4kbit EEPROM
FEATURES
• Selectable watchdog timer
• Low VCC detection and reset assertion
—Five standard reset threshold voltages
—Adjust low VCC reset threshold voltage using
special programming sequence
—Reset signal valid to VCC = 1V
• Low power CMOS
—<20µA max standby current, watchdog on
—<1µA standby current, watchdog OFF
—3mA active current
• 4kbits of EEPROM
—16-byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2, all or 16, 32, 64 or 128 bytes
of EEPROM array with Block Lockprotection
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
www.DataSheet4U.com Available packages
—8 Ld SOIC
—8 Ld MSOP
—8 Ld PDIP
• Pb-free plus anneal available (RoHS compliant)
BLOCK DIAGRAM
DESCRIPTION
The X4043/45 combines four popular functions,
Power-on Reset Control, Watchdog Timer, Supply
Voltage Supervision, and Block Lock Protect Serial
EEPROM Memory in one package. This combination
lowers system cost, reduces board space require-
ments, and increases reliability.
Applying power to the device activates the power-on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the
RESET/RESET signal. The user selects the interval
from three preset values. Once selected, the interval
does not change, even after cycling the power.
The device’s low VCC detection circuitry protects the
user’s system from low voltage conditions, resetting the
system when VCC falls below the minimum VCC trip
point. RESET/RESET is asserted until VCC returns to
proper operating level and stabilizes. Five industry stan-
dard VTRIP thresholds are available, however, Intersil’s
unique circuits allow the threshold to be reprogrammed
to meet custom requirements or to fine-tune the thresh-
old for applications requiring higher precision.
WP
SDA
SCL
VCC
Watchdog Transition
Detector
Data
Register
Command
Decode &
Control
Logic
VCC Threshold
Reset logic
Protect Logic
Status
Register
EEPROM Array
VTRIP
+
-
Watchdog
Timer Reset
Reset &
Watchdog
Timebase
Power-on and
Low Voltage
Reset
Generation
RESET (X4043)
RESET (X4045)
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.




X4043 pdf, 반도체, 판매, 대치품
X4043, X4045
The memory portion of the device is a CMOS Serial
EEPROM array with Intersil’s block lock protection.
The array is internally organized as x 8. The device
features an 2-wire interface and software protocol
allowing operation on an I2C bus.
The device utilizes Intersil’s proprietary Direct Write
cell, providing a minimum endurance of 1,000,000
cycles and a minimum data retention of 100 years.
PIN CONFIGURATION
8-Pin JEDEC SOIC, MSOP, PDIP
NC
NC
RESET
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
Pin
(SOIC/MSOP/DIP)
1
2
3
4
5
6
7
8
Name
NC
NC
RESET/RESET
VSS
SDA
SCL
WP
VCC
Function
No internal connections
No internal connections
Reset Output. RESET is an active LOW, open drain output which goes active
whenever VCC falls below VTRIP. It will remain active until VCC rises above the
VTRIP for tPURST. RESET/RESET goes active if the Watchdog Timer is enabled
and SDA remains either HIGH or LOW longer than the selectable Watchdog time
out period. RESET/RESET goes active on power-uppower-up and remains
active for 250ms after the power supply stabilizes. RESET is an active high open
drain output. An external pull up resistor is required on the RESET/RESET pin.
Ground
Serial Data. SDA is a bidirectional pin used to transfer data into and out of the
device. It has an open drain output and may be wire ORed with other open drain
or open collector outputs. This pin requires a pull up resistor and the input buffer
is always active (not gated).
Serial Clock. The Serial Clock input controls the serial bus timing for data input and
output.
Write Protect. WP HIGH prevents writes to any location in the device (including
the control register). Connect WP pin to VSS when it is not used.
Supply Voltage
4 FN8118.1
September 30, 2005

4페이지










X4043 전자부품, 판매, 대치품
X4043, X4045
Figure 3. Reset VTRIP Level Sequence (VCC > 3V. WP = 15-18V, WEL bit set)
WP VP = 15-18V
SCL
0 1 23 4 56 7
0 1 23 4 56 7
0 1 23 4 56 7
SDA
A0h
Figure 4. Sample VTRIP Reset Circuit
VTRIP
Adj.
4.7K
RESET
03h
1
2
3 X4043
4
8
7
6
5
00h
VP
Adjust
Run
µC
SCL
SDA
7 FN8118.1
September 30, 2005

7페이지


구       성 총 24 페이지수
다운로드[ X4043.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
X40410

(X40410 - X40415) Dual Voltage Monitor

Intersil Corporation
Intersil Corporation
X40411

(X40410 - X40415) Dual Voltage Monitor

Intersil Corporation
Intersil Corporation

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵