X40435 Datasheet PDF - Intersil Corporation
| Part Number | X40435 | |
| Description | (X40430 - X40435) Triple Voltage Monitor | |
| Manufacturers | Intersil Corporation | |
| Logo |  |
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X40430, X40431, X40434, X40435
® 4Kbit EEPROM
Data Sheet
July 29, 2005
FN8251.0
Triple Voltage Monitor with Integrated
CPU Supervisor
FEATURES
• Monitoring voltages: 5V to 9V
• Independent core voltage monitor
• Triple voltage detection and reset assertion
—Standard reset threshold settings. See selec-
tion table on page 2.
—Adjust low voltage reset threshold voltages
using special programming sequence
—Reset signal valid to VCC = 1V
—Monitor three separate voltages
• Fault detection register
• Selectable power-on reset timeout
(0.05s, 0.2s, 0.4s, 0.8s)
• Selectable watchdog timer interval
(25ms, 200ms, 1.4s or off)
• Debounced manual reset input
• Low power CMOS
—25µA typical standby current, watchdog on
—6µA typical standby current, watchdog off
• Memory security
•www.DataSheet4U.com 4Kbits of EEPROM
—16 byte page write mode
—5ms write cycle time (typical)
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Block lock protect 0, or 1/2, of EEPROM
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available packages
—14-lead SOIC, TSSOP
APPLICATIONS
• Communication Equipment
—Routers, Hubs, Switches
—Disk Arrays, Network Storage
• Industrial Systems
—Process Control
—Intelligent Instrumentation
• Computer Systems
— Computers
—Network Servers
DESCRIPTION
The X40430, X40431, X40434, X40435 combines
power-on reset control, watchdog timer, supply voltage
supervision, second and third voltage supervision,
manual reset, and Block Lock™ protect serial EEPROM
in one package. This combination lowers system cost,
reduces board space requirements, and increases
reliability.
Applying voltage to VCC activates the power-on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and system oscilla-
tor to stabilize before the processor can execute code.
Low VCC detection circuitry protects the user’s system
from low voltage conditions, resetting the system
when VCC falls below the minimum VTRIP1 point.
RESET/RESET is active until VCC returns to proper
operating level and stabilizes. A second and third volt-
age monitor circuit tracks the unregulated supply to
provide a power fail warning or monitors different
power supply voltage. Three common low voltage
combinations are available. However, Intersil’s unique
circuits allows the threshold for either voltage monitor
to be reprogrammed to meet specific system level
requirements or to fine-tune the threshold for applica-
tions requiring higher precision.
A manual reset input provides debounce circuitry for
minimum reset component count.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the WDO signal.
The user selects the interval from three preset values.
Once selected, the interval does not change, even
after cycling the power.
The memory portion of the device is a CMOS Serial
EEPROM array with Intersil’s Block Lock protection.
The array is internally organized as x 8. The device
features a 2-wire interface and software protocol
allowing operation on an I2C bus.
The device utilizes Intersil’s proprietary Direct Write™
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
|
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X40430, X40431, X40434, X40435
Figure 3. VTRIPX Set/Reset Conditions
VTRIPX
(X = 1, 2, 3)
VCC/V2MON/V3MON
WDO
VP
SCL 0
70
70
7
SDA
A0h
WATCHDOG TIMER
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the SDA and SCL pins. A
standard read or write sequence to any slave address
byte restarts the watchdog timer and prevents the
WDO signal going active. A minimum sequence to
reset the watchdog timer requires four microprocessor
instructions namely, a Start, Clock Low, Clock High
and Stop. The state of two nonvolatile control bits in
the Status Register determine the watchdog timer
period. The microprocessor can change these watch-
dog bits by writing to the X40430, X40431, X40434,
X40435 control register (also refer to page 20).
Figure 4. Watchdog Restart
.6µs
1.3µs
SCL
SDA
Start
WDT Reset Stop
V1, V2 AND V3 THRESHOLD PROGRAM
PROCEDURE (OPTIONAL)
The X40430 is shipped with standard V1, V2 and V3
threshold (VTRIP1, VTRIP2, VTRIP3) voltages. These
values will not change over normal operating and stor-
age conditions. However, in applications where the
standard thresholds are not exactly right, or if higher
precision is needed in the threshold value, the X40430,
X40431, X40434, X40435 trip points may be adjusted.
The procedure is described below, and uses the appli-
cation of a high voltage control signal.
5
00h tWC
Setting a VTRIPx Voltage (x = 1, 2, 3)
There are two procedures used to set the threshold
voltages (VTRIPx), depending if the threshold voltage
to be stored is higher or lower than the present value.
For example, if the present VTRIPx is 2.9 V and the
new VTRIPx is 3.2 V, the new voltage can be stored
directly into the VTRIPx cell. If however, the new setting
is to be lower than the present setting, then it is neces-
sary to “reset” the VTRIPx voltage before setting the
new value.
Setting a Higher VTRIPx Voltage (x = 1, 2, 3)
To set a VTRIPx threshold to a new voltage which is
higher than the present threshold, the user must apply
the desired VTRIPx threshold voltage to the corre-
sponding input pin Vcc(V1MON), V2MON or V3MON.
Then, a programming voltage (Vp) must be applied to the
WDO pin before a START condition is set up on SDA.
Next, issue on the SDA pin the Slave Address A0h, fol-
lowed by the Byte Address 01h for VTRIP1, 09h for
VTRIP2, and 0Dh for VTRIP3, and a 00h Data Byte in order
to program VTRIPx. The STOP bit following a valid write
operation initiates the programming sequence. Pin WDO
must then be brought LOW to complete the operation. To
check if the VTRIPX has been set, set VXMON to a value
slightly greater than VTRIPX (that was previously set).
Slowly ramp down VXMON and observe when the corre-
sponding outputs (LOWLINE, V2FAIL and V3FAIL)
switch. The voltage at which this occurs is the VTRIPX
(actual).
FN8251.0
July 29, 2005
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| Information | Total 24 Pages | |
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| Download | [ X40435.PDF Datasheet ] | |
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