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X40430 데이터시트 PDF




Xicor에서 제조한 전자 부품 X40430은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 X40430 기능
기능 (X40430 / X40431) Triple Voltage Monitor
제조업체 Xicor
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X40430 데이터시트, 핀배열, 회로
Preliminary Information
4kbit EEPROM
X40430/X40431
Triple Voltage Monitor with Integrated CPU Supervisor
FEATURES
• Triple voltage detection and reset assertion
—Three standard reset threshold settings
(4.6V/2.9V/1.7V, 4.4V/2.6V/1.7V,
2.9V/1.7V/2.4V)
—Adjust low voltage reset threshold voltages
using special programming sequence
—Reset signal valid to VCC = 1V
—Monitor three voltages or detect power fail
• Fault detection register
• Selectable power on reset timeout
• Selectable watchdog timer interval
• Debounced manual reset input
• Low power CMOS
—30µA typical standby current, watchdog on
—10µA typical standby current, watchdog off
• 4Kbits of EEPROM
—16 byte page write mode
—Self-timed write cycle
www.DataSheet4U.com — 5ms write cycle time (typical)
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Block lock protect 0, 1/4, 1/2, all of EEPROM
• 400kHz I2C interface
• 2.4V to 5.5V power supply operation
• Available packages
—14-lead SOIC, TSSOP
BLOCK DIAGRAM
DESCRIPTION
The X40430/31 combines power-on reset control,
watchdog timer, supply voltage supervision, secondary
and third voltage supervision, manual reset, and Block
Lockprotect serial EEPROM in one package. This
combination lowers system cost, reduces board space
requirements, and increases reliability.
Applying voltage to VCC activates the power on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and system oscillator
to stabilize before the processor can execute code.
Low VCC detection circuitry protects the user’s system
from low voltage conditions, resetting the system when
VCC falls below the minimum VTRIP1 point. RESET/
RESET is active until VCC returns to proper operating
level and stabilizes. A second and third voltage monitor
circuit tracks the unregulated supply to provide a
power fail warning or monitors different power supply
voltage. Three common low voltage combinations are
available, however, Xicor’s unique circuits allows the
threshold for either voltage monitor to be repro-
grammed to meet special needs or to fine-tune the
threshold for applications requiring higher precision.
V3MON
V2MON
V3 Monitor
Logic
+
VTRIP3
-
V2 Monitor
Logic
+
VTRIP2
-
V3FAIL
V2FAIL
SDA
WP
SCL
VCC
(V1MON)
Data
Register
Command
Decode Test
& Control
Logic
REV 1.2.3 11/28/00
Fault Detection
Register
Status
Register
EEPROM
Array
VCCLoMgoicnitor
+
VTRIP1
-
www.xicor.com
Watchdog
and
Reset Logic
WDO
MR
Power on,
Manual Reset
Low Voltage
Reset
Generation
RESET
X40430
RESET
X40431
LOWLINE
Characteristics subject to change without notice. 1 of 24




X40430 pdf, 반도체, 판매, 대치품
X40430/X40431 – Preliminary Information
Low Voltage VCC (V1 Monitoring)
During operation, the X40430 monitors the VCC level
and asserts RESET if supply voltage falls below a pre-
set minimum VTRIP1. The RESET signal prevents the
microprocessor from operating in a power fail or
brownout condition. The RESET/RESET signal
remains active until the voltage drops below 1V. It also
remains active until VCC returns and exceeds VTRIP1
for tPURST.
Low Voltage V2 Monitoring
The X40430 also monitors a second voltage level and
asserts V2FAIL if the voltage falls below a preset mini-
mum VTRIP2. The V2FAIL signal is either ORed with
RESET to prevent the microprocessor from operating
in a power fail or brownout condition or used to inter-
rupt the microprocessor with notification of an impend-
ing power failure. The V2FAIL signal remains active
until the V2MON drops below 1V (V2MON falling). It
also remains active until V2MON returns and exceeds
VTRIP2 by 0.2V.
Low Voltage V3 Monitoring
The X40430 also monitors a third voltage level and
asserts V3FAIL if the voltage falls below a preset mini-
mum VTRIP3. The V3FAIL signal is either ORed with
RESET to prevent the microprocessor from operating
in a power fail or brownout condition or used to inter-
rupt the microprocessor with notification of an impend-
ing power failure. The V3FAIL signal remains active
until the V3MON drops below 1V (V3MON falling). It
also remains active until V3MON returns and exceeds
VTRIP3 by 0.2V.
Early Low VCC Detection (LOWLINE)
This CMOS output goes LOW earlier than RESET/
RESET whenever VCC falls below the VTRIP1 voltage
and returns high when VCC exceeds the VTRIP1 volt-
age. There is no power up delay circuitry (tPURST) on
this pin.
Figure 2. Two Uses of Multiple Voltage Monitoring
Unreg.
Supply
R
R
X40430
5V VCC
Reg RESET
V2MON
V2FAIL
V2MON
System
Reset
Resistors selected so 3V appears on V2MON when unregulated
supply reaches 6V.
Unreg.
Supply
5V
Reg
4V
Reg
3V
Reg
X40431
V2MON
VCC V3MON
VCC
RESET
V2MON
V2FAIL
System
Reset
V3MON
V3FAIL
Notice: No external components required to monitor three voltages.
REV 1.2.3 11/28/00
www.xicor.com
Characteristics subject to change without notice. 4 of 24

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X40430 전자부품, 판매, 대치품
X40430/X40431 – Preliminary Information
Figure 6. VTRIP Set/Reset Sequence (X = 1, 2, 3)
VTRIPX Programming
No Desired
VTRIPX
Present Value
YES
Execute
VTRIP Reset Sequence
New VX applied =
Old VX applied + Error
NO
Execute
Set Higher VTRIP Sequence
Execute
Set Higher VX Sequence
Apply VCC and Voltage
Desired VTRIPX to VX
Decrease VX
New VX applied =
Old VX applied - Error
Execute Reset VTRIPX
Sequence
Error < -MDE
Output Switches?
YES
Actual VTRIPX –
Desired VTRIPX
Error < | MDE |
DONE
Error > +MDE
Vx = VCC, V2MON, V3MON
Note: X = 1, 2, 3
Let: MDE = Maximum Desired Error
WEL: Write Enable Latch (Volatile)
The WEL bit controls the access to the memory and to
the Register during a write operation. This bit is a vola-
tile latch that powers up in the LOW (disabled) state.
While the WEL bit is LOW, writes to any address,
including any control registers will be ignored (no
acknowledge will be issued after the Data Byte). The
WEL bit is set by writing a “1” to the WEL bit and
zeroes to the other bits of the control register.
Once set, WEL remains set until either it is reset to 0
(by writing a “0” to the WEL bit and zeroes to the other
bits of the control register) or until the part powers up
again. Writes to the WEL bit do not cause a high volt-
age write cycle, so the device is ready for the next
operation immediately after the stop condition.
REV 1.2.3 11/28/00
www.xicor.com
Characteristics subject to change without notice. 7 of 24

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