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FOD260L 데이터시트 PDF




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부품번호 FOD260L 기능
기능 (FOD060L - FOD260L) LVTTL/LVCMOS 3.3V High Speed-10 MBit/s Logic Gate Optocouplers
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FOD260L 데이터시트, 핀배열, 회로
June 2005
FOD060L, FOD260L, FOD063L
LVTTL/LVCMOS 3.3V High Speed-10 MBit/s
Logic Gate Optocouplers
Single Channel: FOD060L, FOD260L
Dual Channel: FOD063L
Features
Compact SO8 package (except FOD260L – 8-pin DIP)
Very high speed – 10 MBit/s
Superior CMR — 50 kV/µs at 2,000V peak
Fan-out of 8 over -40°C to +85°C
Logic gate output
Strobable output (single channel devices)
Wired OR-open collector
U.L. recognized (File # E90700) (pending)
UDE approval pending
Applications
Ground loop elimination
LSTTL to TTL, LSTTL or 5-volt CMOS
Line receiver, data transmission
Data multiplexing
Switching power supplies
Pulse transformer replacement
Computer-peripheral interface
Description
These optocouplers consist of an AlGaAS LED, optically cou-
pled to a very high speed integrated photo-detector logic gate.
Single channel devices include a strobable output. This output
features an open collector, thereby permitting wired OR outputs.
The output consists of bipolar transistors in a Bi-CMOS process
for reduced power consumption. The coupled parameters are
guaranteed over the temperature range of -40°C to +85°C. A
maximum input signal of 5 mA (3 mA for the FODX6XL ver-
sions) will provide a minimum output sink current of 13 mA (fan
out of 8). An internal noise shield provides superior common
mode rejection of typically 50 kV/µs at 2,000V common mode.
Package
8
1
8
1
8
1
N/C 1
+2
VF
_3
N/C 4
8 VCC
7 VE
6 VO
5 GND
+1
V
F1
_2
_3
V
F2
+4
8
V
CC
7
V
01
6V
02
5 GND
Single-channel circuit drawing Dual-channel circuit drawing
(FOD060L, FOD260L)
(FOD063L)
Truth Table (Positive Logic)
Input
H
L
H
L
H*
L*
Enable
H
H
L
L
NC*
NC*
Output
L
H
H
H
L*
H*
*Dual channel devices or single channel devices with pin 7 not connected.
A 0.1 µF bypass capacitor must be connected between pins 8 and 5. (See note 1)
©2005 Fairchild Semiconductor Corporation
FOD060L, FOD260L, FOD063L Rev. 1.0.0
1
www.fairchildsemi.com




FOD260L pdf, 반도체, 판매, 대치품
Transfer Characteristics (TA = -40°C to +85°C Unless otherwise specified.)
DC Characteristics
Test Conditions Symbol Min Typ**
High Level Output Current
Low Level Output Voltage
Input Threshold Current
(IF = 250 µA, VCC = 3.3 V, VO = 3.3 V)
(Note 2) VE = 2.0 V Single Channel
(VCC = 3.3 V, IF = 5 mA, IOL = 13 mA)
(Note 2) VE = 2.0 V Single Channel
(VCC = 3.3 V, VO = 0.6 V, IOL = 13 mA)
(Note 2) VE = 2.0 V Single Channel
IOH
VOL
IFT
Max
50
0.6
5
Unit
µA
V
mA
Isolation Characteristics (TA = -40°C to +85°C Unless otherwise specified.)
Characteristics
Test Conditions Device Symbol Min Typ** Max Unit
Input-Output
Insulation Leakage Current
(Relative humidity = 45%)
(TA = 25°C, t = 5 s)
(VI-O = 3000 VDC)
(Note 12)
II-O
1.0* µA
Withstand Insulation Test
Voltage
Resistance (Input to Output)
Capacitance (Input to Output)
IIO 10 µA, RH < 50%,
TA = 25°C)
(Note 12) ( t = 1 min.)
FOD060L
FOD063L
FOD260L
(VI-O = 500 V) (Note 12)
(f = 1 MHz) (Note 12)
VISO
RI-O
CI-O
2500
5000
1012
0.6
VRMS
pF
** All typical values are at VCC = 3.3 V, TA = 25°C
Notes
1. The VCC supply to each optoisolator must be bypassed by a 0.1µF capacitor or larger. This can be either a ceramic or solid
tantalum capacitor with good high frequency characteristic and should be connected as close as possible to the package VCC and
GND pins of each device.
2. Enable Input – No pull up resistor required as the device has an internal pull up resistor.
3. tPLH – Propagation delay is measured from the 3.75 mA level on the HIGH to LOW transition of the input current pulse to the
1.5V level on the LOW to HIGH transition of the output voltage pulse.
4. tPHL – Propagation delay is measured from the 3.75 mA level on the LOW to HIGH transition of the input current pulse to the 1.5V
level on the HIGH to LOW transition of the output voltage pulse.
5. tPSK is the worst case difference between tPHL and tPLH for any devices at the stated test conditions.
6. tr – Rise time is measured from the 90% to the 10% levels on the LOW to HIGH transition of the output pulse.
7. tf – Fall time is measured from the 10% to the 90% levels on the HIGH to LOW transition of the output pulse.
8. tELH – Enable input propagation delay is measured from the 1.5V level on the HIGH to LOW transition of the input voltage pulse
to the 1.5V level on the LOW to HIGH transition of the output voltage pulse.
9. tEHL – Enable input propagation delay is measured from the 1.5V level on the LOW to HIGH transition of the input voltage pulse
to the 1.5V level on the HIGH to LOW transition of the output voltage pulse.
10. CMH – The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the high state (i.e.,
VOUT > 2.0 V). Measured in volts per microsecond (V/µs).
11. CML – The maximum tolerable rate of fall of the common mode voltage to ensure the output will remain in the low output state
(i.e., VOUT < 0.8 V). Measured in volts per microsecond (V/µs).
12. Device considered a two-terminal device: Pins 1,2,3 and 4 shorted together, and Pins 5,6,7 and 8 shorted together.
FOD060L, FOD260L, FOD063L Rev. 1.0.0
4
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FOD260L 전자부품, 판매, 대치품
Pulse Gen.
tf = tr = 5 ns
ZO = 50
1
Input
Monitor
(IF)
47
2
3
4
VCC 8
7
0.1µF
Bypass
6
GND 5
Test Circuit for FOD060L,
and FOD260L
+3.3V
Pulse Gen.
ZO = 50
tf = tr = 5 ns
IF
Input
RL Monitoring
Node
Output
(VO)
CL
RM
Dual Channel
1 VCC 8
27
36
45
GND
+3.3V
RL
0.1µF
Bypass
Output VO
Monitoring
Node
CL*
Input
(I F)
tPHL
Output
(VO)
Output
(VO)
Test Circuit for FOD063L
tf
I F = 7.5 mA
I F = 3.75 mA
tPLH
90%
10 %
1.5 V
tr
Fig. 9 Test Circuit and Waveforms for tPLH, tPHL, tr and tf.
Pulse
Generator
tr = 5ns
ZO = 50
1
7.5 mA
2
3
4
Input
Monitor
(VE)
8
7
0.1µF
bypass
6
5
+3.3V
RL
Output
(VO)
CL
Input
(VE )
tEHL
Output
(VO)
Fig. 10 Test Circuit tEHL and tELH.
t ELH
3.0 V
1.5 V
1.5 V
FOD060L, FOD260L, FOD063L Rev. 1.0.0
7
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FOD260L

(FOD060L - FOD260L) LVTTL/LVCMOS 3.3V High Speed-10 MBit/s Logic Gate Optocouplers

Fairchild Semiconductor
Fairchild Semiconductor

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