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부품번호 | X5168 기능 |
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기능 | (X5168 / X5169) CPU Supervisor | ||
제조업체 | Intersil Corporation | ||
로고 | |||
전체 20 페이지수
®
Data Sheet
X5168, X5169
(Replaces X25268, X25169)
June 15, 2006
FN8130.2
CPU Supervisor with 16Kbit SPI EEPROM
These devices combine three popular functions, Power-on
Reset Control, Supply Voltage Supervision, and Block Lock
Protect Serial EEPROM Memory in one package. This
combination lowers system cost, reduces board space
requirements, and increases reliability.
Applying power to the device activates the power-on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and oscillator to stabilize
before the processor can execute code.
The device’s low VCC detection circuitry protects the user’s
system from low voltage conditions by holding
RESET/RESET active when VCC falls below a minimum VCC
trip point. RESET/RESET remains asserted until VCC returns
to proper operating level and stabilizes. Five industry
standard VTRIP thresholds are available, however, Intersil’s
unique circuits allow the threshold to be reprogrammed to
meet custom requirements or to fine-tune the threshold in
applications requiring higher precision.
www.DataSheet4U.com
Block Diagram
WP
SI
SO
SCK
CS
Data
Register
Command
Decode &
Control
Logic
Features
• Low VCC Detection and Reset Assertion
- Five standard reset threshold voltages
- Re-program low VCC reset threshold voltage using
special programming sequence
- Reset signal valid to VCC = 1V
• Long Battery Life with Low Power Consumption
- <50µA max standby current, watchdog on
- <1µA max standby current, watchdog off
- <400µA max active current during read
• 16Kbits of EEPROM
• Built-in Inadvertent Write Protection
- Power-up/power-down protection circuitry
- Protect 0, 1/4, 1/2 or all of EEPROM array with Block
Lock™ protection
- In circuit programmable ROM mode
• 2MHz SPI Interface Modes (0,0 & 1,1)
• Minimize EEPROM Programming Time
- 32-byte page write mode
- Self-timed write cycle
- 5ms write cycle time (typical)
• 2.7V to 5.5V and 4.5V to 5.5V Power Supply
Operation
• Available Packages
- 14 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP
• Pb-Free Plus Anneal Available (RoHS Compliant)
Protect Logic
Status
Register
4Kbits
4Kbits
8Kbits
VCC
VTRIP
+
-
Reset
Timebase
Power-on and
Low Voltage
Reset
Generation
RESET/RESET
X5168 = RESET
X5169 = RESET
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X5168, X5169
Pin Description
PIN
(SOIC/PDIP)
1
PIN TSSOP
1
22
58
69
36
47
8 14
7 13
3-5,10-12
NAME
CS
SO
SI
SCK
WP
VSS
VCC
RESET/
RESET
NC
FUNCTION
Chip Select Input. CS HIGH, deselects the device and the SO output
pin is at a high impedance state. Unless a nonvolatile write cycle is underway, the device will be
in the standby power mode. CS LOW enables the device, placing it in the active power mode. Prior
to the start of any operation after power-up, a HIGH to LOW transition on CS is required.
Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The
falling edge of the serial clock (SCK) clocks the data out.
Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this
pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1),
addresses and data MSB first.
Serial Clock. The serial clock controls the serial bus timing for data input and output. The rising edge
of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of SCK
changes the data output on the SO pin.
Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting
of the watchdog timer control and the memory write protect bits.
Ground
Supply Voltage
Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which goes active
whenever VCC falls below the minimum VCC sense level. It will remain active until VCC rises above
the minimum VCC sense level for 200ms. RESET/RESET goes active if the watchdog timer is
enabled and CS remains either HIGH or LOW longer than the selectable watchdog time out
period. A falling edge of CS will reset the watchdog timer. RESET/RESET goes active on power-
up at about 1V and remains active for 200ms after the power supply stabilizes.
No internal connections
4 FN8130.2
June 15, 2006
4페이지 X5168, X5169
SPI Serial Memory
The memory portion of the device is a CMOS serial
EEPROM array with Intersil’s block lock protection. The
array is internally organized as x 8. The device features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus.
The device utilizes Intersil’s proprietary Direct Write™ cell,
providing a minimum endurance of 100,000 cycles and a
minimum data retention of 100 years.
The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families. It contains an 8-bit
instruction register that is accessed via the SI input, with
data being clocked in on the rising edge of SCK. CS must be
LOW during the entire operation.
All instructions (Table 1), addresses and data are transferred
MSB first. Data input on the SI line is latched on the first
rising edge of SCK after CS goes LOW. Data is output on the
SO line by the falling edge of SCK. SCK is static, allowing
the user to stop the clock and then start it again to resume
operations where left off.
Write Enable Latch
The device contains a write enable latch. This latch must be
SET before a write operation is initiated. The WREN
instruction will set the latch and the WRDI instruction will
reset the latch (Figure 3). This latch is automatically reset
upon a power-up condition and after the completion of a
valid write cycle.
Status Register
The RDSR instruction provides access to the status register.
The status register may be read at any time, even during a
write cycle. The status register is formatted as follows:
7
WPEN
6
FLB
5
0
4 3210
0 BL1 BL0 WEL WIP
The Write-In-Progress (WIP) bit is a volatile, read only bit
and indicates whether the device is busy with an internal
nonvolatile write operation. The WIP bit is read using the
RDSR instruction. When set to a “1”, a nonvolatile write
operation is in progress. When set to a “0”, no write is in
progress.
INSTRUCTION NAME
WREN
SFLB
WRDI/RFLB
RDSR
WRSR
READ
WRITE
TABLE 1. INSTRUCTION SET
INSTRUCTION FORMAT*
OPERATION
0000 0110
Set the write enable latch (enable write operations)
0000 0000
Set flag bit
0000 0100
Reset the write enable latch/reset flag bit
0000 0101
Read status register
0000 0001
Write status register (watchdog, block lock, WPEN and flag bits)
0000 0011
Read data from memory array beginning at selected address
0000 0010
Write data to memory array beginning at selected address
Note: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
WREN CMD
WEL
0
1
1
1
STATUS REGISTER
WPEN
X
1
0
X
TABLE 2. BLOCK PROTECT MATRIX
DEVICE PIN
BLOCK
BLOCK
WP#
X
0
X
1
PROTECTED BLOCK
Protected
Protected
Protected
Protected
UNPROTECTED BLOCK
Protected
Writable
Writable
Writable
STATUS REGISTER
WPEN, BL0, BL1 WD0,
WD1
Protected
Protected
Writable
Writable
7 FN8130.2
June 15, 2006
7페이지 | |||
구 성 | 총 20 페이지수 | ||
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부품번호 | 상세설명 및 기능 | 제조사 |
X5163 | CPU Supervisor with 16Kbit SPI EEPROM | Xicor |
X5163 | (X5163 / X5165) CPU Supervisor | Intersil Corporation |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |