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PDF X9241A Data sheet ( Hoja de datos )
| Número de pieza | X9241A | |
| Descripción | Quad Digital Controlled Potentionmeters | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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X9241A
®
Quad Digital Controlled Potentionmeters (XDCP™)
Data Sheet
December 14, 2006
FN8164.5
Non-Volatile/Low Power/2-Wire/64 Taps
The X9241A integrates four digitally controlled
potentiometers (XDCP) on a monolithic CMOS integrated
microcircuit.
The digitally controlled potentiometer is implemented using
63 resistive elements in a series array. Between each
element are tap points connected to the wiper terminal
through switches. The position of the wiper on the array is
controlled by the user through the 2-wire bus interface. Each
potentiometer has associated with it a volatile Wiper Counter
Register (WCR) and 4 nonvolatile Data Registers
(DR0:DR3) that can be directly written to and read by the
user. The contents of the WCR controls the position of the
wiper on the resistor array through the switches. Power up
recalls the contents of DR0 to the WCR.
The XDCP can be used as a three-terminal potentiometer or
as a two-terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
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Block Diagram
Features
• Four potentiometers in one package
• 2-wire serial interface
• Register oriented format
- Direct read/write/transfer of wiper positions
- Store as many as four positions per potentiometer
• Terminal Voltages: +5V, -3.0V
• Cascade resistor arrays
• Low power CMOS
• High Reliability
- Endurance–100,000 data changes per bit per register
- Register data retention–100 years
• 16-bytes of nonvolatile memory
• 3 resistor array values
- 2kΩ, 10kΩ, 50kΩ or combination
- Cascadable for values of 4kΩ to 200kΩ
• Resolution: 64 taps each pot
• 20 Ld plastic DIP, 20 Ld TSSOP and 20 Ld SOIC
packages
• Pb-free plus anneal available (RoHS compliant)
VCC
VSS
SCL
SDA
A0
A1
A2
A3
Interface
and
Control
Circuitry
8
Data
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
VH0/RH0
VL0/RL0
VW0/RW0
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
Register
Array
Pot 2
VH2/
RH2
VL2/RL2
VW2/RW2
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
Register
Array
Pot 1
VH1/RH1
VL1/RL1
VW1/RW1
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
Register
Array
Pot 3
VH3/RH3
VL3/RL3
VW3/RW3
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
X9241A
Flow 1. ACK Polling Sequence
Nonvolatile Write
Command Completed
Enter ACK Polling
Issue
START
Issue Slave
Address
ACK
Returned?
Yes
No
FurTher
OperaTion?
Yes
Issue
Instruction
No
Issue STOP
Issue STOP
Proceed
Proceed
Instruction Structure
The next byte sent to the X9241A contains the instruction
and register pointer information. The four most significant
bits are the instruction. The next four bits point to one of four
pots and when applicable they point to one of four
associated registers. The format is shown below in Figure 2.
Potentiometer
Select
I3 I2 I1 I0 P1 P0 R1 R0
The four high order bits define the instruction. The next two
bits (P1 and P0) select which one of the four potentiometers
is to be affected by the instruction. The last two bits (R1 and
R0) select one of the four registers that is to be acted upon
when a register oriented instruction is issued.
Four of the nine instructions end with the transmission of the
instruction byte. The basic sequence is illustrated in Figure
3. These two-byte instructions exchange data between the
WCR and one of the data registers. A transfer from a Data
Register to a WCR is essentially a write to a static RAM. The
response of the wiper to this action will be delayed tSTPWV.
A transfer from WCR current wiper position, to a Data
Register is a write to nonvolatile memory and takes a
minimum of tWR to complete. The transfer can occur
between one of the four potentiometers and one of its
associated registers; or it may occur globally, wherein the
transfer occurs between all four of the potentiometers and
one of their associated registers.
Four instructions require a three-byte sequence to complete.
These instructions transfer data between the host and the
X9241A; either between the host and one of the Data
Registers or directly between the host and the WCR. These
instructions are: Read WCR, read the current wiper position
of the selected pot; Write WCR, change current wiper
position of the selected pot; Read Data Register, read the
contents of the selected nonvolatile register; Write Data
Register, write a new value to the selected Data Register.
The sequence of operations is shown in Figure 4.
The Increment/Decrement command is different from the
other commands. Once the command is issued and the
X9241A has responded with an acknowledge, the master
can clock the selected wiper up and/or down in one segment
steps; thereby, providing a fine tuning capability to the host.
For each SCL clock pulse (tHIGH) while SDA is HIGH, the
selected wiper will move one resistor segment towards the
VH/RH terminal. Similarly, for each SCL clock pulse while
SDA is LOW, the selected wiper will move one resistor
segment towards the VL/RL terminal. A detailed illustration
of the sequence and timing for this operation are shown in
Figures 5 and 6 respectively.
Instructions
Register
Select
FIGURE 2. INSTRUCTION BYTE FORMAT
5 FN8164.5
December 14, 2006
5 Page 
X9241A
Endurance and Data Retention
PARAMETER
Minimum endurance
Data retention
MIN
100,000
100
UNIT
Data changes per bit per register
Years
Capacitance
SYMBOL
PARAMETER
CI/O (Note 5)
CIN (Note 5)
Input/output capacitance (SDA)
Input capacitance (A0, A1, A2, A3 and SCL)
TEST CONDITION
VI/O = 0V
VIN = 0V
TYP
19
12
UNIT
pF
pF
Power-up Timing
SYMBOL
PARAMETER
tPUR (Note 6)
tPUW (Note 6)
tRVCC
Power-up to initiation of read operation
Power-up to initiation of write operation
VCC Power up ramp rate
MIN TYP MAX
1
5
0.2 50
UNIT
ms
ms
V/ms
Power-up Requirements (Power Up sequencing can affect correct recall of the wiper registers)
The preferred power-on sequence is as follows: First VCC, then the potentiometer pins. It is suggested that Vcc reach 90% of its
final value before power is applied to the potentiometer pins. The VCC ramp rate specification should be met, and any glitches or
slope changes in the VCC line should be held to <100mV if possible. Also, VCC should not reverse polarity by more than 0.5V.
Notes: (5) This parameter is not 100% tested.
(6) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters are
guaranteed by design.
(7) This parameter is guaranteed by design.
(8) Maximum Wiper Current is derated over temperature. See the Wiper Current Derating Curve.
(9) Ti value denotes the maximum noise glitch pulse width that the device will ignore on either SCL or SDA pins. Any noise glitch pulse
width that is greater than this maximum value will be considered as a valid clock or data pulse and may cause communication failure to
the device.
Equivalent AC Test Circuit
AC Conditions of Test
Input pulse levels
VCC x 0.1 to VCC x 0.9
5V
Input rise and fall times
10ns
1533Ω
Input and output timing levels
VCC x 0.5
SDA Output
Symbol Table
100pF
WAVEFORM
INPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
OUTPUTS
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
Circuit #3 SPICE Macro Model
Macro Model
RTOTAL
RH RL
CH CL
15pF
CW 15pF
25pF
RW
11 FN8164.5
December 14, 2006
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet X9241A.PDF ] | |
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