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X9269 데이터시트 PDF




Intersil Corporation에서 제조한 전자 부품 X9269은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 X9269 자료 제공

부품번호 X9269 기능
기능 Dual Digitally-Controlled Potentiometers
제조업체 Intersil Corporation
로고 Intersil Corporation 로고


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X9269 데이터시트, 핀배열, 회로
NOTPROESCSOIBMLMEESNUDBXES9DT5FI8T®O2U0RTENEPWRDOaDDtEaUSSCIGhTeNeSt
X9269
Single Supply/Low Power/256-Tap/2-Wire Bus
April 17, 2007
FN8173.4
Dual Digitally-Controlled (XDCP™)
Potentiometers
FEATURES
• Dual–Two Separate Potentiometers
• 256 Resistor Taps/Pot–0.4% Resolution
• 2-Wire Serial Interface for Write, Read, and
Transfer Operations of the Potentiometer Single
Supply Device
Wiper Resistance, 100Ω Typical VCC = 5V
• 4 Nonvolatile Data Registers for Each
Potentiometer
• Nonvolatile Storage of Multiple Wiper Positions
• Power-on Recall. Loads Saved Wiper Position
on Power-up.
• Standby Current < 5µA Max
• 50kΩ, 100kΩ Versions of End to End Pot
Resistance
• 100 yr. Data Retention
• Endurance: 100,000 Data Changes per Bit per
Register
• 24-Lead SOIC, 24-Lead TSSOP
• Low Power CMOS
www.DataSheet4U.com Power Supply VCC = 2.7V to 5.5V
• Pb-Free Plus Anneal Available (RoHS Compliant)
DESCRIPTION
The X9269 integrates 2 digitally controlled
potentiometer (XDCP) on a monolithic CMOS
integrated circuit.
The digital controlled potentiometer is implemented
using 255 resistive elements in a series array.
Between each element are tap points connected to the
wiper terminal through switches. The position of the
wiper on the array is controlled by the user through the
2-Wire bus interface. Each potentiometer has
associated with it a volatile Wiper Counter Register
(WCR) and a four nonvolatile Data Registers that can
be directly written to and read by the user. The
contents of the WCR controls the position of the wiper
on the resistor array though the switches. Powerup
recalls the contents of the default Data Register (DR0)
to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
FUNCTIONAL DIAGRAM
VCC
RH0
RH1
2-Wire
Bus
Interface
Address
Data
Status
Bus
Interface
and Control
Write
Read
Transfer
Inc/Dec
Control
Power-on Recall
Wiper Counter
Registers (WCR)
Data Registers
(DR0–DR3)
VSS
RW0 RL0 RW1 RL1
50kΩ or 100kΩ versions
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006, 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.




X9269 pdf, 반도체, 판매, 대치품
PIN CONFIGURATION
SOIC/TSSOP
NC
A0
NC
NC
NC
NC
VCC
RL0
RH0
RW0
A2
WP
1 24
2 23
3 22
4 21
5 20
6 19
7 X9269 18
8 17
9 16
10 15
11 14
12 13
A3
SCL
NC
NC
NC
NC
VSS
RW1
RH1
RL1
A1
SDA
X9269
PIN ASSIGNMENTS
Pin
(SOIC/TSSOP)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Symbol
NC
A0
NC
NC
NC
NC
VCC
RL0
RH0
RW0
A2
WP
SDA
A1
RL1
RH1
RW1
VSS
NC
NC
NC
NC
SCL
A3
Function
No Connect
Device Address for 2-Wire bus.
No Connect
No Connect
No Connect
No Connect
System Supply Voltage
Low Terminal for Potentiometer 0.
High Terminal for Potentiometer 0.
Wiper Terminal for Potentiometer 0.
Device Address for 2-Wire bus.
Hardware Write Protect
Serial Data Input/Output for 2-Wire bus.
Device Address for 2-Wire bus.
Low Terminal for Potentiometer 1.
High Terminal for Potentiometer 1.
Wiper Terminal for Potentiometer 1.
System Ground
No Connect
No Connect
No Connect
No Connect
Serial Clock for 2-Wire bus.
Device Address for 2-Wire bus.
4
FN8173.4
April 17, 2007

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X9269 전자부품, 판매, 대치품
X9269
SERIAL INTERFACE DESCRIPTION
Serial Interface
The X9269 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9269 will be considered a
slave device in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW periods. SDA state changes during SCL
HIGH are reserved for indicating start and stop
conditions. See Figure 2.
Start Condition
All commands to the X9269 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH. The X9269 continuously monitors
the SDA and SCL lines for the start condition and will
not respond to any command until this condition is
met. See Figure 2.
Figure 2. Acknowledge Response from Receiver
Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH. See Figure 2.
Acknowledge
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.
The X9269 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9269 will respond with a final acknowledge.
See Figure 2.
SCL FROM
MASTER
DATA
OUTPUT
FROM
TRANSMITTER
DATA
OUTPUT
FROM
RECEIVER
START
1
89
ACKNOWLEDGE
7 FN8173.4
April 17, 2007

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