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PDF X9401 Data sheet ( Hoja de datos )
| Número de pieza | X9401 | |
| Descripción | Digitally Controlled Potentiometer | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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®
Data Sheet
X9401
Low Noise/Low Power/SPI Bus
October 12, 2006
FN8190.3
Quad, 64 Tap, Digitally Controlled
Potentiometer (XDCP™)
FEATURES
• Quad–4 separate pots, 64 taps/pot
• Nonvolatile storage of wiper position
• Four Nonvolatile Data Registers for Each Pot
• 16-bytes of EEPROM memory
• SPI serial interface
• RTotal = 10kΩ
• Wiper resistance = 150Ω typical
• Standby current < 1µA (total package)
• Operating current < 400µA max.
• VCC = 2.7V to 5V
• Package–24 Ld SOIC
• 100 year data retention
• Pb-free plus anneal available (RoHS compliant)
DESCRIPTION
The X9401 integrates 4 digitally controlled potentiome-
ters (XDCP) on a monolithic CMOS integrated
microcircuit.
The digitally controlled potentiometer is implemented
using 64 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the SPI bus
interface. Each potentiometer has associated with it a
volatile Wiper Counter Register (WCR) and 4 nonvola-
tile Data Registers (DR0:DR3) that can be directly writ-
ten to and read by the user. The contents of the WCR
controls the position of the wiper on the resistor array
through the switches. Power-up recalls the contents of
DR0 to the WCR.
The XDCP can be used as a three-terminal potentiom-
eter or as a two-terminal variable resistor in a wide
variety of applications including control, parameter
adjustments, and signal processing.
BLOCK DIAGRAM
www.DataSheet4U.com
VCC
VSS
HOLD
CS
SCK
SO
SI
A0
A1
WP
Interface
and
Control
Circuitry
8
Data
R0 R1
R2 R3
Pot 0
Wiper
Counter
Register
(WCR)
VH0/RH0
VL0/RL0
VW0/RW0
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 2
VH2/RH2
VL2/RL2
VW2/RW2
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
VW1/RW1
Resistor
Array
Pot 1
VH1/RH1
VL1/RL1
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
VW3/RW3
Resistor
Array
Pot 3
VH3/RH3
VL3/RL3
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
X9401
one of the data registers or directly between the host
and the Wiper Counter Register. These instructions
are:
– Read Wiper Counter Register— read the current
wiper position of the selected pot,
– Write Wiper Counter Register—change current
wiper position of the selected pot,
– Read Data Register—read the contents of the
selected data register;
– Write Data Register—write a new value to the
selected data register.
– Read Status—This command returns the contents
of the WIP bit which indicates if the internal write
cycle is in progress.
The sequence of these operations is shown in Figure 4
and Figure 5.
The final command is Increment/Decrement. It is dif-
ferent from the other commands, because it’s length is
indeterminate. Once the command is issued, the mas-
ter can clock the selected wiper up and/or down in one
resistor segment steps; thereby, providing a fine tun-
ing capability to the host. For each SCK clock pulse
(tHIGH) while SI is HIGH, the selected wiper will move
one resistor segment towards the VH/RH terminal.
Similarly, for each SCK clock pulse while SI is LOW,
the selected wiper will move one resistor segment
towards the VL/RL terminal. A detailed illustration of the
sequence and timing for this operation are shown in
Figure 6 and Figure 7.
Detailed Potentiometer Block Diagram
(One of Four Arrays)
Serial Data Path
From Interface
Circuitry
Register 0
8
Register 2
If WCR = 00[H] then VW/RW = VL/RL
If WCR = 3F[H] then VW/RW = VH/RH
Register 1
6
Register 3
Serial
Bus
Input
Parallel
Bus
Input
Wiper
Counter
Register
(WCR)
UP/DN
Modified SCL
INC/DEC
Logic
UP/DN
CLK
C
o
u
n
t
e
r
D
e
c
o
d
e
VH/RH
VL/RL
VW/RW
5 FN8190.3
October 12, 2006
5 Page 
X9401
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Symbol
Parameter
ICC1 VCC supply current (active)
ICC2
ISB
VCC supply current (nonvola-
tile write)
VCC current (standby)
ILI Input leakage current
ILO Output leakage current
VIH Input HIGH voltage
VIL Input LOW voltage
VOL Output LOW voltage
Min.
Limits
Typ. Max.
400
1
1
VCC x 0.7
-0.5
10
10
VCC + 0.5
VCC x 0.1
0.4
Unit
µA
mA
µA
µA
µA
V
V
V
Test Conditions
fSCK = 2MHz, SO = Open,
Other Inputs = VSS
fSCK = 2MHz, SO = Open,
Other Inputs = VSS
SCK = SI = VSS, Addr. = VSS,
CS = VCC
VIN = VSS to VCC
VOUT = VSS to VCC
IOL = 3mA
ENDURANCE AND DATA RETENTION
Parameter
Minimum endurance
Data retention
Min.
100,000
100
Unit
Data changes per bit per register
years
CAPACITANCE
Symbol
COUT(4)
CIN(4)
Test
Output capacitance (SO)
Input capacitance (A0, A1, SI, and SCK)
POWER-UP TIMING
Symbol
tr VCC(6)
tPUR(5)
tPUW(5)
Parameter
VCC Power-up rate
Power-up to initiation of read operation
Power-up to initiation of write operation
A.C. TEST CONDITIONS
Input pulse levels
Input rise and fall times
Input and output timing level
VCC x 0.1 to VCC x 0.9
10ns
VCC x 0.5
Notes: (4) This parameter is periodically sampled and not 100%
tested
(5) tPUR and tPUW are the delays required from the time
the (last) power supply (VCC-) is stable until the specific
instruction can be issued. These parameters are period-
ically sampled and not 100% tested.
(6) This is not a tested or guaranteed parameter and should
be used only as a guideline.
Max.
8
6
Unit
pF
pF
Test Condition
VOUT = 0V
VIN = 0V
Min.
0.2
Max.
50
1
5
EQUIVALENT A.C. LOAD CIRCUIT
Unit
V/ms
ms
ms
SDA
Output
5V
1533Ω
100pF
SPICE Macro Model
RTOTAL
RH
CL CW
10pF
25pF
RW
RL
CL
10pF
11 FN8190.3
October 12, 2006
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet X9401.PDF ] | |
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