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부품번호 | X9409 기능 |
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기능 | Quad Digitally Controlled Potentiometers | ||
제조업체 | Intersil Corporation | ||
로고 | |||
전체 19 페이지수
DATASHEET
Low Noise/Low Power/2-Wire Bus Quad Digitally
Controlled Potentiometers (XDCP™)
X9409
The X9409 integrates 4 digitally controlled potentiometers
(XDCP) on a monolithic CMOS integrated microcircuit.
The digitally controlled potentiometer is implemented using
63 resistive elements in a series array. Between each element
are tap points connected to the wiper terminal through
switches. The position of the wiper on the array is controlled by
the user through the 2-wire bus interface. Each potentiometer
has associated with it a volatile Wiper Counter Register (WCR)
and 4 nonvolatile Data Registers (DR0:DR3) that can be
directly written to and read by the user. The contents of the
WCR controls the position of the wiper on the resistor array
through the switches. Power-up recalls the contents of DR0 to
the WCR.
The XDCP can be used as a three-terminal potentiometer or as
a two-terminal variable resistor in a wide variety of
applications including control, parameter adjustments and
signal processing.
Features
• Four potentiometers per package
• 64 resistor taps
• 2-wire serial interface for write, read and transfer operations
of the potentiometer
• 50Ω wiper resistance, typical at 5V
• Four nonvolatile data registers for each potentiometer
• Nonvolatile storage of multiple wiper position
• Power-on recall. Loads saved wiper position on power-up
standby current < 1µA typical
• System VCC: 2.7V operation
• 10kΩ end-to-end resistance
• 100 year data retention
• Endurance: 100,000 data changes per bit per register
• Low power CMOS
• 24 Ld TSSOP
• Pb-free (RoHS compliant)
VCC
VSS
WP
SCL
SDA
A0
A1
A2
A3
INTERFACE
AND
CONTROL
CIRCUITRY
8
DATA
POT 0
R0 R1
WIPER
COUNTER
REGISTER
R2 R3
(WCR)
VH0/RHO
VL0/
RLO
VW0/
RWO
R0 R1 WIPER
COUNTER
REGISTER
R2 R3
(WCR)
RESISTOR
ARRAY
POT 2
VH2/RH2
VL2/RL2
VW2/RW2
R0 R1
R2 R3
WIPER
COUNTER
REGISTER
(WCR)
RESISTOR
ARRAY
POT 1
VW1/
RW1
VH1/
RH1
VL1/RL1
VW3/RW3
R0 R1
R2 R3
WIPER
COUNTER
REGISTER
(WCR)
RESISTOR
ARRAY
Pot 3
VH3/RH3
VL3/RL3
FIGURE 1. BLOCK DIAGRAM
September 3, 2015
FN8192.6
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2005-2006, 2015. All Rights Reserved
Intersil (and design) and XDCP are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
Symbol Table
WAVEFORM INPUTS
OUTPUTS
Must be
steady
May change
from Low to
High
May change
from High to
Low
Don’t Care:
Changes
Allowed
N/A
Will be
steady
Will change
from Low to
High
Will change
from High to
Low
Changing:
State Not
Known
Center Line
is High
Impedance
X9409
Guidelines for Calculating
Typical Values of Bus Pull-Up
Resistors
120
100 RMIN = VCC MAX = 1.8kΩ
I OL MIN
80
60
RMAX =
tR
CBUS
40
MAX.
RESISTANCE
20 MIN.
RESISTANCE
0
0 20 40 60 80
BUS CAPACITANCE (pF)
100
120
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FN8192.6
September 3, 2015
4페이지 X9409
AC TIMING Across recommended operating conditions. (Continued)
SYMBOL
tSU:WPA
tHD:WPA
PARAMETER
WP, A0, A1, A2 and A3 Setup Time
WP, A0, A1, A2 and A3 Hold Time
MIN
(Note 6)
0
MAX
(Note 6)
0
UNITS
ns
HIGH-VOLTAGE WRITE CYCLE TIMING
SYMBOL
tWR
PARAMETER
High-Voltage Write Cycle Time (Store Instructions)
MAX
TYP
(Note 6)
UNIT
5 10 ms
XDCP TIMING
SYMBOL
PARAMETER
MIN
(Note 6)
MAX
TYP (Note 6) UNITS
tWRPO
Wiper Response Time After The Third (Last) Power Supply Is Stable
2 10 µs
tWRL
Wiper Response Time After Instruction Issued (All Load Instructions)
2 10 µs
tWRID
Wiper Response Time From An Active SCL/SCK Edge (Increment/Decrement Instruction)
2 10 µs
NOTES:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
7. Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
8. Relative Linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a
measure of the error in step size.
9. MI = RTOT/63 or (VH - VL)/63, single pot.
10. This parameter is periodically sampled and not 100% tested.
11. Sample tested only.
12. A device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL.
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FN8192.6
September 3, 2015
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구매 문의 | 일반 IC 문의 : 샘플 및 소량 구매 ----------------------------------------------------------------------- IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한 광범위한 전력 반도체를 판매합니다. 전력 반도체 전문업체 상호 : 아이지 인터내셔날 사이트 방문 : [ 홈페이지 ] [ 블로그 1 ] [ 블로그 2 ] |
부품번호 | 상세설명 및 기능 | 제조사 |
X9400 | Quad Digitally Controlled Potentiometers (XDCP) | Xicor |
X9400 | Quad Digitally Controlled Potentiometers | Intersil Corporation |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |