|
|
PDF X9523 Data sheet ( Hoja de datos )
| Número de pieza | X9523 | |
| Descripción | Laser Diode Control | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de X9523 (archivo pdf) en la parte inferior de esta página. Total 28 Páginas | ||
|
No Preview Available !
NOc1NoT-8nOR8ta8ERc-CEItNOCoTMOuErMMRTMESeNIEcLDhNonEDr®iDcEwaDFwl OSRwRuE.ipPnDNpLtEaeoAtrWrasCt iCESlD.cMehEoneSEmteINeGt/rTtNsacSt
Dual DCP, POR, Dual Voltage Monitors
FEATURES
• Two Digitally Controlled Potentiometers (DCPs)
—100 Tap - 10kΩ
—256 Tap - 100kΩ
— Nonvolatile
—Write Protect Function
• 2-Wire Industry Standard Serial Interface
• Power-On Reset (POR) Circuitry
—Programmable Threshold Voltage
—Software Selectable reset timeout
—Manual Reset
• Two Supplementary Voltage Monitors
—Programmable Threshold Voltages
• Single Supply Operation
—2.7V to 5.5V
• Hot Pluggable
• 20 Pin Package
— TSSOP
• Pb-Free Plus Anneal Available (RoHS Compliant)
X9523
Laser Diode Control for Fiber Optic Modules
January 3, 2006
FN8209.1
DESCRIPTION
The X9523 combines two Digitally Controlled Potenti-
ometers (DCPs), V1 / Vcc Power-on Reset (POR) cir-
cuitry, qnd two programmable voltage monitor inputs
with software and hardware indicators. All functions of
the X9523 are accessed by an industry standard 2-Wire
serial interface.
The DCPs of the X9523 may be utilized to control the
bias and modulation currents of the laser diode in a Fiber
Optic module. The programmable POR circuit may be
used to ensure that V1 / Vcc is stable before power is
applied to the laser diode / module. The programmable
voltage monitors may be used for monitoring various
module alarm levels.
The features of the X9523 are ideally suited to simpli-
fying the design of fiber optic modules . The integra-
tion of these functions into one package significantly
reduces board area, cost and increases reliability of
laser diode modules.
www.DataSheet4U.com
BLOCK DIAGRAM
WP
SDA
SCL
MR
V3
V2
V1 / Vcc
DATA
REGISTER
COMMAND
DECODE &
CONTROL
LOGIC
THRESHOLD
RESET LOGIC
PROTECT LOGIC
8
CONSTAT
REGISTER
VTRIP3
VTRIP 2
VTRIP1
-
+
-
+
+
-
2
WIPER
COUNTER
REGISTER
7 - BIT
NONVOLATILE
MEMORY
WIPER
COUNTER
REGISTER
8 - BIT
NONVOLATILE
MEMORY
POWER-ON /
LOW VOLTAGE
RESET
GENERATION
RH1
RW1
RL1
RH2
RW2
RL2
V3RO
V2RO
V1RO
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
©2000 Intersil Inc., Patents Pending. Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
X9523
SCL
from
Master
Data Output
from
Transmitter
1
89
Data Output
from
Receiver
Start
Acknowledge
Figure 3. Acknowledge Response From Receiver
minate further data transmissions if an ACKNOWLEDGE
is not detected. The master must then issue a STOP
condition to place the device into a known state.
DEVICE INTERNAL ADDRESSING
Addressing Protocol Overview
The user addressable internal components of the X9523
can be split up into two main parts:
—Two Digitally Controlled Potentiometers (DCPs)
—Control and Status (CONSTAT) Register
Depending upon the operation to be performed on
each of these individual parts, a 1, 2 or 3 Byte proto-
col is used. All operations however must begin with
the Slave Address Byte being issued on the SDA pin.
The Slave address selects the part of the X9523 to
be addressed, and specifies if a Read or Write opera-
tion is to be performed.
It should be noted that in order to perform a write opera-
tion to a DCP, the Write Enable Latch (WEL) bit must first
be set (See “WEL: Write Enable Latch (Volatile)” on
page 10.).
Slave Address Byte
Following a START condition, the master must output a
Slave Address Byte (Refer to Figure 4.). This byte con-
sists of three parts:
—The Device Type Identifier which consists of the most
significant four bits of the Slave Address (SA7 - SA4).
The Device Type Identifier must always be set to 1010
in order to select the X9523.
—The next three bits (SA3 - SA1) are the Internal Device
Address bits. Setting these bits to 111 internally
selects the DCP structures in the X9523. The CON-
STAT Register may be selected using the Internal
Device Address 010.
—The Least Significant Bit of the Slave Address (SA0)
Byte is the R/W bit. This bit defines the operation to be
performed on the device being addressed (as defined
in the bits SA3 - SA1). When the R/W bit is “1”, then a
READ operation is selected. A “0” selects a WRITE
operation (Refer to Figure 4.)
Nonvolatile Write Acknowledge Polling
After a nonvolatile write command sequence (for either
the Non Volatile Memory of a DCP (NVM), or the CON-
STAT Register) has been correctly issued (including the
SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0
101 0
R/W
DEVICE TYPE
IDENTIFIER
Internal Address
(SA3 - SA1)
010
111
All Others
INTERNAL
DEVICE
ADDRESS
READ /
WRITE
Internally Addressed
Device
CONSTAT Register
DCP
RESERVED
Bit SA0
0
1
Operation
WRITE
READ
Figure 4. Slave Address Format
5 FN8209.1
January 3, 2006
5 Page 
X9523
SCL
SDA
S 1 0 1 0 0 1 0 R/W A 1
TC
AK
R
T
SLAVE ADDRESS BYTE
1 11 1 1 1 1
ADDRESS BYTE
A CS7 CS6 CS5 CS4 CS3 CS2 CS1 CS0 A S
C CT
K KO
CONSTAT REGISTER DATA IN
P
Figure 13. CONSTAT Register Write Command Sequence
POR1, POR0: Power-on Reset bits - (Nonvolatile)
Applying voltage to VCC activates the Power-on Reset
circuit which holds V1RO output HIGH, until the supply
voltage stabilizes above the VTRIP1 threshold for a
period of time, tPURST (See Figure 25).
The Power-on Reset bits, POR1 and POR0 of the
CONSTAT register determine the tPURST delay time of
the Power-on Reset circuitry (See "VOLTAGE MONI-
TORING FUNCTIONS"). These bits of the CONSTAT
register are nonvolatile, and therefore power-up to the
last written state.
The nominal Power-on Reset delay time can be selected
from the following table, by writing the appropriate bits to
the CONSTAT register:
POR1
0
0
1
1
POR0
0
1
0
1
Power-on Reset delay (tPUV1RO)
50ms
100ms (Default)
200ms
300ms
The default for these bits are POR1 = 0, POR0 = 1.
V2OS, V3OS: Voltage Monitor Status Bits (Volatile)
Bits V2OS and V3OS of the CONSTAT register are
latched, volatile flag bits which indicate the status of the
Voltage Monitor reset output pins V2RO and V3RO.
At power-up the VxOS (x = 2,3) bits default to the value
“0”. These bits can be set to a “1” by writing the appropri-
ate value to the CONSTAT register. To provide consis-
tency between the VxRO and VxOS however, the status
of the VxOS bits can only be set to a “1” when the corre-
sponding VxRO output is HIGH.
Once the VxOS bits have been set to “1”, they will be
reset to “0” if:
—The device is powered down, then back up,
—The corresponding VxRO output becomes LOW.
CONSTAT Register Write Operation
The CONSTAT register is accessed using the Slave
Address set to 1010010 (Refer to Figure 4.). Following
the Slave Address Byte, access to the CONSTAT regis-
ter requires an Address Byte which must be set to FFh.
Only one data byte is allowed to be written for each
CONSTAT register Write operation. The user must issue
a STOP, after sending this byte to the register, to initiate
the nonvolatile cycle that stores the DWLK, POR1 and
POR0 bits. The X9523 will not ACKNOWLEDGE any
data bytes written after the first byte is entered (Refer to
Figure 13.).
When writing to the CONSTAT register, the bit CS4 must
always be set to “0”. Writing a “1” to bit CS4 of the CON-
STAT register is a reserved operation.
Prior to writing to the CONSTAT register, the WEL and
RWEL bits must be set using a two step process, with
the whole sequence requiring 3 steps
—Write a 02H to the CONSTAT Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation preceded
by a START and ended with a STOP).
—Write a 06H to the CONSTAT Register to set the Reg-
ister Write Enable Latch (RWEL) AND the WEL bit.
This is also a volatile cycle. The zeros in the data byte
are required. (Operation preceded by a START and
ended with a STOP).
11 FN8209.1
January 3, 2006
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet X9523.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| X9520 | Dual Voltage Monitors | Intersil Corporation |
| X9521 | Dual DCP/ EEPROM Memory |  Xicor |
| X9521 | EEPROM Memory | Intersil Corporation |
| X9522 | Dual Voltage Monitors | Intersil Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |