X98017 Datasheet PDF - Intersil Corporation
| Part Number | X98017 | |
| Description | 170MHz Triple Video Digitizer | |
| Manufacturers | Intersil Corporation | |
| Logo |  |
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There is a preview and X98017 download ( pdf file ) link at the bottom of this page. Total 29 Pages | ||
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NTOHTERISELC9OI8MM0P0M1RE-O1N7VD0EEIDSDAAFLO1T®R0E0RN%NECAWOTDDIMVaEEPtSaAIGTSINhBSeLeE-t
170MHz Triple Video Digitizer with
Digital PLL
The X98017 3-channel, 8-bit Analog Front End (AFE)
contains all the components necessary to digitize analog
RGB or YUV graphics signals from personal computers,
workstations and video set-top boxes. The fully differential
analog design provides high PSRR and dynamic
performance to meet the stringent requirements of the
graphics display industry. The AFE’s 170MSPS conversion
rate supports resolutions up to UXGA at 60Hz refresh rate,
while the front end's high input bandwidth ensures sharp
images at the highest resolutions.
To minimize noise, the X98017's analog section features 2
sets of pseudo-differential RGB inputs with programmable
input bandwidth, as well as internal DC restore clamping
(including mid-scale clamping for YUV signals). This is
followed by the programmable gain/offset stage and the
three 170MSPS Analog-to-Digital Converters (ADCs).
Automatic Black Level Compensation (ABLC™) eliminates
part-to-part offset variation, ensuring perfect black level
performance in every application.
The X98017's digital PLL generates a pixel clock from the
analogwww.DataSheet4U.com source's HSYNC or SOG (Sync-On-Green) signals.
Pixel clock output frequencies range from 10MHz to 170MHz
with sampling clock jitter of 250ps peak to peak.
Simplified Block Diagram
March 8, 2006
X98017
FN8218.3
Features
• 170MSPS maximum conversion rate
• Low PLL clock jitter (250ps p-p @ 170MSPS)
• 64 interpixel sampling positions
• 0.35Vp-p to 1.4Vp-p video input range
• Programmable bandwidth (100MHz to 780MHz)
• 2 channel input multiplexer
• RGB and YUV 4:2:2 output formats
• 5 embedded voltage regulators allow operation from
single 3.3V supply and enhance performance, isolation
• Completely independent 8 bit gain/10 bit offset control
• CSYNC and SOG support
• Trilevel sync detection
• 1.05W typical PD @ 170MSPS
• Pb-free plus anneal available (RoHS compliant)
Applications
• LCD Monitors and Projectors
• Digital TVs
• Plasma Display Panels
• RGB Graphics Processing
• Scan Converters
RGB/YPbPrIN 1
RGB/YPbPrIN 2
3
3
Voltage
Clamp
PGA
Offset
DAC
ABLC™
+ 8 bit ADC
SOGIN1/2
HSYNCIN1/2
VSYNCIN1/2
Sync
Processing
Digital PLL
AFE Configuration and Control
8 or 16
RGB/YUVOUT
x3
HSYNCOUT
VSYNCOUT
HSOUT
PIXELCLKOUT
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
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X98017
Electrical Specifications Specifications apply for VA = VD = VX = 3.3V, pixel rate = 170MHz, fXTAL = 25MHz, TA = 25°C,
unless otherwise noted (Continued)
SYMBOL
PARAMETER
COMMENT
MIN TYP MAX
tSETUP DATA valid before rising edge of DATACLK 15pF DATACLK load, 15pF DATA load
(Note 1)
1.3
tHOLD DATA valid after rising edge of DATACLK 15pF DATACLK load, 15pF DATA load
(Note 1)
2.0
AC TIMING CHARACTERISTICS (2 WIRE INTERFACE)
fSCL
SCL Clock Frequency
Maximum width of a glitch on SCL that will 2 XTAL periods min
be suppressed
0 400
80
tAA SCL LOW to SDA Data Out Valid
5 XTAL periods plus SDA’s RC time
constant
See
comment
tBUF
Time the bus must be free before a new
transmission can start
1.3
tLOW Clock LOW Time
tHIGH Clock HIGH Time
tSU:STA Start Condition Setup Time
tHD:STA Start Condition Hold Time
tSU:DAT Data In Setup Time
tHD:DAT Data In Hold Time
tSU:STO Stop Condition Setup Time
tDH Data Output Hold Time
4 XTAL periods min
NOTES:
1. Setup and hold times are at a 140MHz DATACLK rate.
1.3
0.6
0.6
0.6
100
0
0.6
160
UNIT
ns
ns
kHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
SCL
SDA IN
tSU:ST
SDA OUT
tF tHIGH
tSU:DAT
tHD:STA
tLOW
tHD:DAT
tR
tAA tDH
FIGURE 1. 2 WIRE INTERFACE TIMING
tSU:STO
tBUF
DATACLK
DATACLK
Pixel Data
tSETUP
tHOLD
FIGURE 2. DATA OUTPUT SETUP AND HOLD TIMING
5
FN8218.3
March 8, 2006
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for X98017 electronic component. |
| Information | Total 29 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ X98017.PDF Datasheet ] | |
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