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PDF AS5C2568 Data sheet ( Hoja de datos )
| Número de pieza | AS5C2568 | |
| Descripción | 32K x 8 SRAM SRAM MEMORY ARRAY | |
| Fabricantes | Austin Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AS5C2568 (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
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Austin Semiconductor, Inc.
SRAM
AS5C2568
32K x 8 SRAM
SRAM MEMORY ARRAY
PIN ASSIGNMENT
(Top View)
FEATURES
• Access Times: 12, 15, & 20ns
• Fast output enable (tDOE) for cache applications
• Low active power: 400 mW (TYP)
• Low power standby
• Fully static operation, no clock or refresh required
• High-performance, low-power CMOS double-metal process
• Single +5V (+10%) Power Supply
• Easy memory expansion with CE\
• All inputs and outputs are TTL compatible
OPTIONS
• Timing
12ns access*
15ns access
20ns access
www.DataSheet4U.com
• Package(s)**
Plastic SOJ
MARKING
-12
-15
-20
DJ No. 906
28-PIN PSOJ (DJ)
A14 1
A12 2
A7 3
A6 4
A5 5
A4 6
A3 7
A2 8
A1 9
A0 10
I/O0 11
I/O1 12
I/O2 13
GND 14
28 VCC
27 WE\
26 A13
25 A8
24 A9
23 A11
22 OE\
21 A10
20 CE\
19 I/O7
18 I/O6
17 I/O5
16 I/O4
15 I/O3
• Operating Temperature Ranges
Military -55oC to +125oC
XT
Industrial -40oC to +85oC
IT
* -12 available in IT only.
** For ceramic version of this product, see the MT5C2568
data sheet.
For more products and information
please visit our web site at
www.austinsemiconductor.com
GENERAL DESCRIPTION
The Austin Semiconductor SRAM family employs
high-speed, low power CMOS designs using a four-transistor
memory cell. These SRAMs are fabricated using double-layer
metal, double-layer polysilicon technology.
For flexibility in high-speed memory applications, Aus-
tin Semiconductor offers chip enable (CE\) and output enable
(OE\) capability. These enhancements can place the outputs in
High-Z for additional flexibility in system design.
Writing to these devices is accomplished when write
enable (WE\) and CE\ inputs are both LOW. Reading is accom-
plished when WE\ remains HIGH and CE\ and OE\ go LOW.
The device offers a reduced power standby mode when dis-
abled. This allows system designs to achieve low standby
power requirements.
All devices operate from a single +5V power supply
and all inputs and outputs are fully TTL compatible.
AS5C2568
Rev. 2.0 12/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
1 page  
Austin Semiconductor, Inc.
AC TEST CONDITIONS
Input pulse levels....................................................Vss to 3V
Input rise and fall times.....................................................5ns
Input timing reference level.............................................1.5V
Output reference level......................................................1.5V
Output load.................................................See figures 1 & 2
Q
255
SRAM
AS5C2568
+5V
480
Q
30 pF
255
+5V
480
5 pF
NOTES
1. All voltages referenced to VSS (GND).
2. -3V for pulse width < 20ns
3. ICC is dependent on output loading and cycle rates. The
specified value applies with the outputs unloaded, and
f = 1 Hz.
tRC (MIN)
4. This parameter is guaranteed but not tested.
5. Test conditions as specified with the output loading as
shown in Fig. 1 unless otherwise noted.
6. t HZCE, tHZOE and tHZWE are specified with CL = 5pF
as in Fig. 2. Transition is measured ±500mV typical from
steady state voltage, allowing for actual tester RC time
constant.
Fig. 1
OUTPUT LOAD
EQUIVALENT
Fig. 2
OUTPUT LOAD
EQUIVALENT
7. At any given temperature and voltage condition, tHZCE
is less than tLZCE, and tHZWE is less than tLZWE.
8. WE\ is HIGH for READ cycle.
9. Device is continuously selected. Chip enables and
output enables are held in their active state.
10. Address valid prior to, or coincident with, latest
occurring chip enable.
11. tRC = Read Cycle Time.
12. Chip enable (CE\) and write enable (WE\) can initiate and
terminate a WRITE cycle.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DESCRIPTION
VCC for Retention Data
Data Retention Current
CONDITIONS
CE\ > (VCC - 0.2V)
VIN > (VCC - 0.2V)
or < 0.2V
VCC = 2V
VCC = 3V
SYMBOL
VDR
ICCDR
MIN
2
MAX
--
1.0
2.0
Chip Deselect to Data
Retention Time
Operation Recovery Time
tCDR
tR
0
tRC
--
UNITS
V
mA
NOTES
mA
ns 4
ns 4, 11
AS5C2568
Rev. 2.0 12/00
LOW Vcc DATA RETENTION WAVEFORM
VCC
tCDR
CE\
VIH
VIL
1111122222333334444455555666667777788888
DATA RETENTION MODE
4.5V
V > 2V
DR
4.5V
tR
VDR
11111222223333344444555551111666662111112227777732222233388888433433344
111122223333DON’T CARE
1111222233334444UNDEFINED
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet AS5C2568.PDF ] | |
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