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PDF AS5SS256K36A Data sheet ( Hoja de datos )
| Número de pieza | AS5SS256K36A | |
| Descripción | 256K x 36 SSRAM Flow-Through Synchronous Burst SRAM | |
| Fabricantes | Austin Semiconductor | |
| Logotipo |  |
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Austin Semiconductor, Inc.
SSRAM
AS5SS256K36 &
AS5SS256K36A
256K x 36 SSRAM
Flow-Through, Synchronous
Burst SRAM
FEATURES
! Organized 256K x 36
! Fast Clock and OE\ access times
! Single +3.3V +0.3V/-0.165V power supply (VDD)
! SNOOZE MODE for reduced-power standby
! Common data inputs and data outputs
! Individual BYTE WRITE control and GLOBAL WRITE
! Three chip enables for simple depth expansion and address
pipelining
! Clock-controlled and registered addresses, data I/Os and
control signals
! Internally self-timed WRITE cycle
! Burst control (interleaved or linear burst)
! Automatic power-down for portable applications
! 100-lead TQFP package for high density, high speed
! Low capacitive bus loading
OPTIONS
Timingwww.DataSheet4U.com !
8.5ns/10ns/100MHz
10ns/15ns/66MHz
! Packages
100-pin TQFP (2-chip enable)
! Pinout
2-chip Enables
3-chip Enables
! Operating Temperature Ranges
Military (-55oC to +125oC)
Industrial (-40oC to +85oC)
MARKING
-8.5*
-10
DQ No. 1001
A (PRELIMINARY)
no indicator
XT*
IT
*NOTE: -8.5/XT combination not available.
GENERAL DESCRIPTION
The AS5SS256K36 employs high-speed, low-power CMOS
designs that are fabricated using an advanced CMOS process.
This 8Mb Synchronous Burst SRAM integrates a 256K x 36
SRAM core with advanced synchronous peripheral circuitry and a 2-bit
burst counter. All synchronous inputs pass through registers controlled
by a positive-edge-triggered single-clock input (CLK). The synchro-
nous inputs include all addresses, all data inputs, active LOW chip en-
able (CE\), two additional chip enables for easy depth expansion (CE2\,
CE2), burst control inputs (ADSC\, ADSP\, ADV\), byte write enables
(BWx\) and global write (GW\). Note that CE2\ is not available on the
A version.
For more products and information
please visit our web site at
www.austinsemiconductor.com
AS5SS256K36 &
AS5SS256K36A
Rev. 3.5 2/03
1
PIN ASSIGNMENT
(Top View)
100-pin TQFP (DQ)
(2-chip enable version, “A” indicator)
DQPc
DQc
DQc
VDDQ
Vss
DQc
DQc
DQc
DQc
Vss
VDDQ
DQc
DQc
Vss
VDD
NC
Vss
DQd
DQd
VDDQ
Vss
DQd
DQd
DQd
DQd
Vss
VDDQ
DQd
DQd
DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
8 0 DQPb
7 9 DQb
7 8 DQb
7 7 VDDQ
7 6 Vss
7 5 DQb
7 4 DQb
7 3 DQb
7 2 DQb
7 1 Vss
7 0 VDDQ
6 9 DQb
6 8 DQb
6 7 Vss
6 6 NC
6 5 VDD
6 4 ZZ
6 3 DQa
6 2 DQa
6 1 VDDQ
6 0 Vss
5 9 DQa
5 8 DQa
5 7 DQa
5 6 DQa
5 5 Vss
5 4 VDDQ
5 3 DQa
5 2 DQa
5 1 DQPa
100-pin TQFP (DQ)
(3-chip enable version, no indicator)
DQPc
DQc
DQc
VDDQ
Vss
DQc
DQc
DQc
DQc
Vss
VDDQ
DQc
DQc
Vss
VDD
NC
Vss
DQd
DQd
VDDQ
Vss
DQd
DQd
DQd
DQd
Vss
VDDQ
DQd
DQd
DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
8 0 DQPb
7 9 DQb
7 8 DQb
7 7 VDDQ
7 6 Vss
7 5 DQb
7 4 DQb
7 3 DQb
7 2 DQb
7 1 Vss
7 0 VDDQ
6 9 DQb
6 8 DQb
6 7 Vss
6 6 NC
6 5 VDD
6 4 ZZ
6 3 DQa
6 2 DQa
6 1 VDDQ
6 0 Vss
5 9 DQa
5 8 DQa
5 7 DQa
5 6 DQa
5 5 Vss
5 4 VDDQ
5 3 DQa
5 2 DQa
5 1 DQPa
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1 page  
Austin Semiconductor, Inc.
SSRAM
AS5SS256K36 &
AS5SS256K36A
INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH)
FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL)
X…X00
X…X01
X…X10
X…X11
X…X01
X…X00
X…X11
X…X10
X…X10
X…X11
X…X00
X…X01
X…X11
X…X10
X…X01
X…X00
LINEAR BURST ADDRESS TABLE (MODE = LOW)
FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL)
X…X00
X…X01
X…X10
X…X11
X…X01
X…X10
X…X11
X…X00
X…X10
X…X11
X…X00
X…X01
X…X11
X…X00
X…X01
X…X10
PARTIAL TRUTH TABLE FOR WRITE COMMANDS
FUNCTION
READ
READ
WRITE Byte "a"
WRITE All Bytes
WRITE All Bytes
GW\
H
H
H
H
L
BWE\
H
L
L
L
X
BWa\
X
H
L
L
X
BWb\
X
H
H
L
X
BWc\
X
H
H
L
X
BWd\
X
H
H
L
X
AS5SS256K36 &
AS5SS256K36A
Rev. 3.5 2/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
5 Page 
Austin Semiconductor, Inc.
SSRAM
AS5SS256K36 &
AS5SS256K36A
SNOOZE MODE
SNOOZE MODE is a low-current, “power-down” mode in
which the device is deselected and current is reduced to ISB2Z.
The duration of SNOOZE MODE is dictated by the length of
time ZZ is in a HIGH state. After the device enters SNOOZE
MODE, all inputs except ZZ become gated inputs and are ig-
nored.
ZZ is an asynchronous, active HIGH input that causes the
device to enter SNOOZE MODE. When ZZ becomes a logic
HIGH, ISB2Z is guaranteed after the setup time tZZ is met. Any
READ or WRITE operation pending when the device enters
SNOOZE MODE is not guaranteed to complete successfully.
Therefore, SNOOZE MODE must not be initiated until valid
pending operations are completed.
SNOOZE MODE ELECTRICAL CHARACTERISTICS
!
NOTE: 1. This parameter is sampled.
AS5SS256K36 &
AS5SS256K36A
Rev. 3.5 2/03
SNOOZE MODE WAVEFORM
CLK
ZZ
ISUPPLY
ALL INPUTS*
*Except ZZ
tZZ tRZZ
tZZI
tSB2
11112222333311114444222255553333444455556666777788881111t992222991111R3333ZZ4444I 5555
11111222223333344444 Don’t Care
11
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet AS5SS256K36A.PDF ] | |
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