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기능 16Mx72 Registered DDR SDRAM
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W3E16M72SR-XBX 데이터시트, 핀배열, 회로
White Electronic Designs
W3E16M72SR-XBX
16Mx72 Registered DDR SDRAM
FEATURES
Registered for enhanced performance of bus
speeds of 200, 225, and 250 MHz
Package:
Auto Refresh and Self Refresh Modes
Commercial, Industrial and Military Temperature
Ranges
• 219 Plastic Ball Grid Array (PBGA), 32 x 25mm
Organized as 16M x 72
2.5V ±0.2V core power supply
Weight: W3E16M72SR-XBX - 2.5 grams typical
2.5V I/O (SSTL_2 compatible)
Differential clock inputs (CK and CK#)
Commands entered on each positive CK edge
Internal pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
Programmable Burst length: 2,4 or 8
Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (one per byte)
DQS edge-aligned with data for READs; center-
www.DataSheet4U.caomligned with data for WRITEs
DLL to align DQ and DQS transitions with CK
BENEFITS
47% SPACE SAVINGS
Glueless Connection to PCI Bridge/Memory
Controller
Reduced part count
Reduced I/O count
• 49% I/O Reduction
Reduced trace lengths for lower parasitic
capacitance
Suitable for hi-reliability applications
Laminate interposer for optimum TCE match
Four internal banks for concurrent operation
Two data mask (DM) pins for masking write data
Upgradeable to 32M x 72 density (contact factory
for information)
Programmable IOL/IOH option
Auto precharge option
* This product is subject to change without notice.
Monolithic Solution
22.3
66
11.9 TSOP
11.9 11.9
22.3
66
TSOP
11.9
8.3
12.6
48
TSOP
66
22.3 TSOP
66
TSOP
66
TSOP
12.6
48
TSOP
Actual Size
S
A
V
White Electronic Designs 25 I
W3E16M72SR-XBX
N
G
32 S
Area
I/O
Count
February 2005
Rev. 2
5 x 265mm2 + 2 x 105mm2 = 1536mm2
5 x 66 pins + 2 x 48 = 426 pins
800mm2
219 Balls
47%
49%
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com




W3E16M72SR-XBX pdf, 반도체, 판매, 대치품
White Electronic Designs
W3E16M72SR-XBX
GENERAL DESCRIPTION
The 128MByte (1Gb) DDR SDRAM is a high-speed CMOS,
dynamic random-access, memory using 5 chips containing
268,435,456 bits. Each chip is internally configured as a
quad-bank DRAM. Each of the chip’s 67,108,864-bit banks
is organized as 8,192 rows by 512 columns by 16 bits.
The 128 MB DDR SDRAM uses a double data rate
architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2n-prefetch
architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write
access for the 128MB DDR SDRAM effectively consists
of a single 2n-bit wide, one-clock-cycle data tansfer at the
internal DRAM core and two corresponding n-bit wide,
one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver. DQS
is a strobe transmitted by the DDR SDRAM during READs
and by the memory contoller during WRITEs. DQS is edge-
aligned with data for READs and center-aligned with data
for WRITEs. Each chip has two data strobes, one for the
lower byte and one for the upper byte.
The 128MB DDR SDRAM operates from a differential clock
(CK and CK#); the crossing of CK going HIGH and CK#
going LOW will be referred to as the positive edge of CK.
Commands (address and control signals) are registered
at every positive edge of CK. Input data is registered on
both edges of DQS, and output data is referenced to both
edges of DQS, as well as to both edges of CK.
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed. The address bits registered
coincident with the READ or WRITE command are used
to select the bank and the starting column location for the
burst access.
The DDR SDRAM provides for programmable READ
or WRITE burst lengths of 2, 4, or 8 locations. An auto
precharge function may be enabled to provide a self-
timed row precharge that is initiated at the end of the
burst access.
The pipelined, multibank architecture of DDR SDRAMs
allows for concurrent operation, thereby providing high
effective bandwidth by hiding row precharge and activation
time.
An auto refresh mode is provided, along with a power-
saving power-down mode.
FUNCTIONAL DESCRIPTION
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank and
row to be accessed (BA0 and BA1 select the bank, A0-12
select the row). The address bits registered coincident
with the READ or WRITE command are used to select the
starting column location for the burst access.
Prior to normal operation, the SDRAM must be initialized.
The following sections provide detailed information
covering device initialization, register definition, command
descriptions and device operation.
INITIALIZATION
DDR SDRAMs must be powered up and initialized in a
predefined manner. Operational procedures other than
those specified may result in undefined operation. Power
must first be applied to VCC and VCCQ simultaneously, and
then to VREF (and to the system VTT). VTT must be applied
after VCCQ to avoid device latch-up, which may cause
permanent damage to the device. VREF can be applied any
time after VCCQ but is expected to be nominally coincident
with VTT. Except for CKE, inputs are not recognized as
valid until after VREF is applied. CKE is an SSTL_2 input
but will detect an LVCMOS LOW level after VCC is applied.
Maintaining an LVCMOS LOW level on CKE during power-
up is required to ensure that the DQ and DQS outputs will
be in the High-Z state, where they will remain until driven
in normal operation (by a read access). After all power
supply and reference voltages are stable, and the clock
is stable, the DDR SDRAM requires a 200µs delay prior
to applying an executable command.
February 2005
Rev. 2
4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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W3E16M72SR-XBX 전자부품, 판매, 대치품
White Electronic Designs
W3E16M72SR-XBX
FIGURE 4 – CAS LATENCY
CLK#
CLK
COMMAND
T0
READ
DQS
DQ
CLK#
CLK
COMMAND
T0
READ
DQS
DQ
T1 T2 T2n T3 T3n
NOP
CL = 2
NOP
NOP
T1 T2 T2n T3 T3n
NOP
CL = 2.5
NOP
NOP
Burst Length = 4 in the cases shown
Shown with nominal tAC and nominal tDSDQ
DATA
TRANSITIONING DATA
DON'T CARE
FIGURE 5 – EXTENDED MODE REGISTER
DEFINITION
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
01 11
Operating Mode
QFC# DS DLL
Extended Mode
Register (Ex)
E0 DLL
0 Enable
1 Disable
E1 Drive Strength
0 Normal
1 Reduced
E22 QFC# Function
0 Disabled
- Reserved
E12 E11 E10 E9 E8 E7 E6 E5 E4 E3
E2, E1, E0
Operating Mode
0000000000
Valid
Reserved
----------
-
Reserved
1. E14 and E13 must be "0, 1" to select the Extended Mode Register (vs. the base Mode Register)
2. The QFE# function is not supported.
OUTPUT DRIVE STRENGTH
The normal full drive strength for all outputs are specified to
be SSTL2, Class II. The DDR SDRAM supports an option
for reduced drive. This option is intended for the support
of the lighter load and/or point-to-point environments. The
selection of the reduced drive strength will alter the DQs
and DQSs from SSTL2, Class II drive strength to a reduced
drive strength, which is approximately 54 percent of the
SSTL2, Class II drive strength.
DLL ENABLE/DISABLE
The DLL must be enabled for normal operation. DLL
enable is required during power-up initialization and upon
returning to normal operation after having disabled the DLL
for the purpose of debug or evaluation. (When the device
exits self refresh mode, the DLL is enabled automatically.)
Any time the DLL is enabled, 200 clock cycles must occur
before a READ command can be issued.
COMMANDS
The Truth Table provides a quick reference of available
commands. This is followed by a written description of
each command.
DESELECT
The DESELECT function (CS# HiGH) prevents new
commands from being executed by the DDR SDRAM. The
SDRAM is effectively deselected. Operations already in
progress are not affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to perform
a NOP to the selected DDR SDRAM (CS# is LOW). This
prevents unwanted commands from being registered
during idle or wait states. Operations already in progress
are not affected.
LOAD MODE REGISTER
The Mode Registers are loaded via inputs A0-12. The LOAD
MODE REGISTER command can only be issued when all
banks are idle, and a subsequent executable command
cannot be issued until tMRD is met.
February 2005
Rev. 2
7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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16Mx72 Registered DDR SDRAM

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