PDF W3EG264M64ETSR-JD3 Data sheet ( Hoja de datos )

Número de pieza	W3EG264M64ETSR-JD3
Descripción	1GB - 2x64Mx64 DDR SDRAM REGISTERED
Fabricantes	White Electronic
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No Preview Available ! White Electronic Designs W3EG264M64ETSR-JD3 ADVANCED* 1GB – 2x64Mx64 DDR SDRAM REGISTERED w/PLL FEATURES Double-data-rate architecture Clock speeds of 133MHz and 166MHz Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2,5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input Auto and self refresh Serial presence detect Dual Rank Power Supply: • VCC = VCCQ = +2.5V (133 and 166MHz) JEDECwww.DataSheet4U.com standard 184 pin DIMM package PCB height: 30.48 (1.20") MAX • JD3: 30.48mm (1.20") DESCRIPTION The W3EG264M64ETSR is a 2x64Mx64 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM component. The module consists of sixteen 64Mx8 DDR SDRAMs in 66 pin TSOP package mounted on a 184 Pin FR4 substrate. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lenths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. * This product is under development, is not qualiﬁed or characterized and is subject to change or cancellation without notice. NOTE: Consult factory for availability of: • RoHS compliant products • Vendor source control options • Industrial temperature option Clock Speed CL-tRCD-tRP OPERATING FREQUENCIES DDR333 @CL=2.5 166MHz 2.5-3-3 DDR266 @CL=2 133MHz 2-3-3 DDR266 @CL=2.5 133MHz 2.5-3-3 April 2005 Rev. 0 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 1 page White Electronic Designs W3EG264M64ETSR-JD3 ADVANCED IDD SPECIFICATIONS AND TEST CONDITIONS Recommended operating conditions, 0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V Includes DDR SDRAM component only Parameter Operating Current Operating Current Precharge Power- Down Standby Current Idle Standby Current Active Power-Down Standby Current Active Standby Current Operating Current Operating Current Auto Refresh Current Self Refresh Current Operating Current Symbol IDD0 IDD1 IDD2P IDD2F IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7A Conditions One device bank; Active - Precharge; tRC=tRC (MIN); tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles. One device bank; Active-Read-Precharge Burst = 2; tRC=tRC (MIN); tCK=tCK (MIN); lOUT = 0mA; Address and control inputs changing once per clock cycle. All device banks idle; Power-down mode; tCK=tCK (MIN); CKE=(low) CS# = High; All device banks idle; tCK=tCK (MIN); CKE = high; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS and DM. One device bank active; Power-Down mode; tCK (MIN); CKE=(low) CS# = High; CKE = High; One device bank; Active- Precharge; tRC=tRAS (MAX); tCK=tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; TCK= TCK (MIN); lOUT = 0mA. Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle. tRC = tRC (MIN) CKE ≤ 0.2V Four bank interleaving Reads (BL=4) with auto precharge with tRC=tRC (MIN); tCK=tCK (MIN); Address and control inputs change only during Active Read or Write commands. DDR333@ CL=2.5 Max 1840 2080 80 720 560 800 2120 2200 3120 80 4040 DDR266@ CL=2 Max 1840 2080 80 720 560 800 2120 2200 3120 80 4040 DDR266@ CL=2.5 Max 1840 2080 80 720 560 800 2120 2200 3120 80 4040 Units mA mA rnA mA mA mA mA rnA mA mA mA April 2005 Rev. 0 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 5 Page White Electronic Designs W3EG264M64ETSR-JD3 ADVANCED PART NUMBERING GUIDE WEDC MEMORY DDR GOLD DEPTH (Dual Rank) BUS WIDTH x8 TSOP 2.5V REGISTERED SPEED (MHz) PACKAGE COMPONENT VENDOR NAME (M = MICRON) (S = SAMSUNG) RoHS COMPLIANT W 3 E G 264M 64 E T S R xxx JD3 x G April 2005 Rev. 0 11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 11 Page

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