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PDF W3EG264M72EFSUXXXD4 Data sheet ( Hoja de datos )
| Número de pieza | W3EG264M72EFSUXXXD4 | |
| Descripción | 1GB - 2x64Mx72 DDR SDRAM | |
| Fabricantes | White Electronic | |
| Logotipo |  |
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White Electronic Designs W3EG264M72EFSUxxxD4
ADVANCED*
1GB – 2x64Mx72 DDR SDRAM, UNBUFFERED, FBGA
FEATURES
Fast data transfer rate: PC-2100, PC-2700 and
PC3200
Clock speeds of 133 MHz, 166 MHz and 200MHz
Supports ECC error detection and correction
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 3 and 4 (clock)
Programmable Burst Length (2, 4 or 8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh
Serial presence detect (SPD) with EEPROM
Dual Rank
VCC = VCCQ = +2.6V (200MHz)
www.DataSheet4U.com
VCC = VCCQ = +2.5V (133 and 166MHz)
Gold edge contacts
JEDEC standard 200 pin, small-outline, SO-DIMM
package
• PCB height option:
31.75 mm (1.25”)
DESCRIPTION
The W3EG264M72EFSU is a 2x64Mx72 Double Data
Rate SDRAM memory module based on 512Mb DDR
SDRAM components. The module consists of eighteen
64Mx8 DDR SDRAMs in FBGA packages mounted on a
200 pin FR4 substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
Clock Speed
CL-tRCD-tRP
OPERATING FREQUENCIES
DDR400@CL=3
200MHz
3-3-3
DDR333@CL=2.5
166MHz
2.5-3-3
DDR266@CL=2
133MHz
2-2-2
DDR266@CL=2.5
133MHz
2.5-3-3
September 2004
Rev. 0
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
1 page  
White Electronic Designs W3EG264M72EFSUxxxD4
ADVANCED
IDD SPECIFICATIONS AND CONDITIONS
0°C ≤ TA ≤ +70°C; VCC, VCCQ = +2.5V ±0.2V
DDR400: VCC = VCCQ = +2.6V ±0.2V
MAX
PARAMETER/CONDITION
SYM DDR400 DDR333 DDR266 DDR266 UNITS
@CL=3 @CL=2.5 @CL=2 @CL=2.5
OPERATING CURRENT: One device bank; Active-Precharge; tRC = tRC (MIN); tCK = tCK
(MIN); DQ, DM and DQS inputs changing once per clock cycle; Address and control inputs
changing once every two clock cycles
IDD0 2475 2070 2070 1845 mA
OPERATING CURRENT: One device bank; Active-Read-Precharge; Burst = 4; tRC = tRC
(MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock
cycle
IDD1 2745 2340 2340 2115 mA
PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down
IDD2P
90
90
90
90
mA
mode; tCK = tCK (MIN); CKE = (LOW)
IDLE STANDBY CURRENT: CS# = HIGH; All device banks are idle; tCK = tCK (MIN); CKE = IDD2F 990 810 810 720 mA
HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ,
DQS, and DM
ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down
mode; tCK = tCK (MIN); CKE = LOW
IDD3P
810
630
630
540
mA
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank active; tRC =
IDD3N 1080
900
900
810
mA
tRAS (MAX); tCK = tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address
and other control inputs changing once per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device bank active;
Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA
IDD4R 2790 2385 2385 2115
mA
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active;
IDD4W 2790 2295 2295 2025
Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS
inputs changing twice per clock cycle
mA
AUTO REFRESH BURST CURRENT:
tREFC = tRFC (MIN)
IDD5 4185 3510 3510 3330 mA
SELF REFRESH CURRENT: CKE ≤ 0.2V
IDD6 90 90 90 90 mA
OPERATING CURRENT: Four device bank interleaving READs (Burst = 4) with auto
precharge, tRC = minimum tRC allowed; tCK = tCK (MIN); Address and control inputs change
only during Active READ, or WRITE commands
IDD7 5130 4545 4545 3960 mA
September 2004
Rev. 0
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
5 Page 
White Electronic Designs W3EG264M72EFSUxxxD4
ADVANCED
PART NUMBERING GUIDE
WEDC
MEMORY
DDR
GOLD
DEPTH (Dual Rank)
BUS WIDTH
x8
FBGA
2.5V
UNBUFFERED
SPEED (MHz)
PACKAGE 200 PIN
W 3 E G 264M 72 E F S U xxx D4
September 2004
Rev. 0
11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet W3EG264M72EFSUXXXD4.PDF ] | |
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