PDF W3EG64128S-D3 Data sheet ( Hoja de datos )

Número de pieza	W3EG64128S-D3
Descripción	1GB - 2x64Mx64 DDR SDRAM UNBUFFERED
Fabricantes	White Electronic
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No Preview Available ! White Electronic Designs W3EG64128S-D3 -JD3 ADVANCED* 1GB – 2x64Mx64 DDR SDRAM UNBUFFERED FEATURES Double-data-rate architecture Clock speeds of 100MHz, 133MHz, 166MHz and 200MHz DDR200, DDR266, DDR333 and DDR400 Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input. Auto and self refresh Serial presence detect Dual Rank Power supply: •www.DataSheet4U.com VCC = VCCQ = +2.5V ±0.2V (100, 133 and 166 MHz) • VCC = VCCQ = +2.6V ±0.1V (200 MHz) JEDEC standard 184 pin DIMM package • JD3 PCB height: 30.48 (1.20") MAX DESCRIPTION The W3EG64128S is a 2x64Mx64 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM component. The module consists of sixteen 64Mx8 DDR SDRAMs in 66 pin TSOP packages mounted on a 184 pin FR4 substrate. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. * This product is under development, is not qualiﬁed or characterized and is subject to change or cancellation without notice. NOTE: Consult factory for availability of: • RoHS compliant products • Vendor source control options • Industrial temperature option Clock Speed CL-tRCD-tRP OPERATING FREQUENCIES DDR400 @ CL=3 200MHz 3-3-3 DDR333 @ CL=2.5 166MHz 2.5-3-3 DDR266 @ CL=2 133MHz 2-2-2 DDR266 @ CL=2 133MHz 2-3-3 DDR266 @ CL=2.5 133MHz 2.5-3-3 DDR200 @ CL=2 100MHz 2-2-2 May 2005 Rev. 5 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 1 page White Electronic Designs W3EG64128S-D3 -JD3 ADVANCED IDD SPECIFICATIONS AND TEST CONDITIONS VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V; DDR400: VCC = VCCQ = +2.6V ± 0.1V Includes DDR SDRAM component only Parameter Symbol Conditions DDR400@ CL=3 Max Operating Current IDD0 One device bank; Active - Precharge; tRC=tRC (MIN); tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles. 2200 Operating Current IDD1 One device bank; Active-Read-Precharge Burst = 2; tRC=tRC (MIN); tCK=tCK (MIN); lOUT = 0mA; Address and control inputs changing once per clock cycle. 2520 Precharge Power- IDD2P All device banks idle; Power-down mode; tCK=tCK Down Standby Current (MIN); CKE=(low) 80 Idle Standby Current IDD2F CS# = High; All device banks idle; tCK=tCK (MIN); CKE = high; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS and DM. 880 Active Power-Down Standby Current IDD3P One device bank active; Power-Down mode; tCK (MIN); CKE=(low) 720 Active Standby Current IDD3N CS# = High; CKE = High; One device bank; Active- Precharge; tRC=tRAS (MAX); tCK=tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. 960 Operating Current IDD4R Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; TCK= TCK (MIN); lOUT = 0mA. 2640 Operating Current IDD4W Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle. 2680 Auto Refresh Current IDD5 tRC = tRC (MIN) 3720 Self Refresh Current IDD6 CKE £ 0.2V 96 Operating Current IDD7A Four bank interleaving Reads (BL=4) with auto precharge with tRC=tRC (MIN); tCK=tCK (MIN); Address and control inputs change only during Active Read or Write commands. 4800 DDR333@ CL=2.5 Max 1840 DDR266@ CL=2 Max 1840 2080 2080 80 80 720 720 560 560 800 800 2120 2120 2360 2080 3120 3120 80 80 4040 4000 DDR266@ CL=2 Max 1840 2080 80 720 560 800 2120 2080 3120 80 4000 DDR266@ CL=2.5 Max 1840 2080 80 720 560 800 2120 2080 3120 80 4000 DDR200@ CL=2 Max 1840 2080 80 720 560 800 2120 2080 3120 80 4000 Units mA mA rnA mA mA mA mA rnA mA mA mA May 2005 Rev. 5 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 5 Page White Electronic Designs W3EG64128S-D3 -JD3 ADVANCED ORDERING INFORMATION FOR D3 Part Number Speed CAS Latency tRCD tRP Height* W3EG64128S403D3 200MHz/266Mb/s 3 33 30.48 (1.20) W3EG64128S335D3 166MHz/333Mb/s 2.5 33 30.48 (1.20) W3EG64128S262D3 133MHz/266Mb/s 2 22 30.48 (1.20") W3EG64128S263D3 133MHz/266Mb/s 2 33 30.48 (1.20) W3EG64128S265D3 133MHz/266Mb/s 2.5 33 30.48 (1.20") W3EG64128S202D3 100MHz/200Mb/s 2 22 30.48 (1.20") NOTES: • Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant) • Vendor speciﬁc part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualiﬁed sourcing options. (M = Micron, S = Samsung & consult factory for others) • Consult factory for availability of industrial temperature (-40°C to 85°C) option PACKAGE DIMENSIONS FOR D3 3.99 (0.157 (2x)) 17.78 (0.700) 10.01 (0.394) 6.35 (0.250) 133.48 (5.255" MAX.) 131.34 (5.171") 128.95 (5.077") 64.77 (2.550) 6.35 (0.250) 1.78 (0.070) 1.27 49.53 (0.050 TYP.) (1.950) 3.81 (0.150 MAX) 30.48 (1.20) MAX 3.99 (0.157) (MIN) 2.31 (0.091) (2x) 3.00 (0.118) (4x) 1.27 ± 0.10 (0.050 ± 0.004) * ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES) May 2005 Rev. 5 11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 11 Page

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