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W3EG6433S-AD4 데이터시트 PDF




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부품번호 W3EG6433S-AD4 기능
기능 256MB - 32Mx64 DDR SDRAM UNBUFFERED
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W3EG6433S-AD4 데이터시트, 핀배열, 회로
White Electronic Designs
W3EG6433S-AD4
-BD4
PRELIMINARY*
256MB - 32Mx64 DDR SDRAM UNBUFFERED, w/PLL
FEATURES
DDR200, DDR266 and DDR333
Double-data-rate architecture
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh
Serial presence detect
Power supply: 2.5V ± 0.20V
JEDEC standard 200 pin SO-DIMM package
• Package height options:
AD4: 35.5mm (1.38")
www.DataSheet4U.com BD4: 31.75mm (1.25")
DESCRIPTION
The W3EG6433S is a 32Mx64 Double Data Rate
SDRAM memory module based on 256Mb DDR
SDRAM component. The module consists of eight
32Mx8 DDR SDRAMs in 66 pin TSOP package
mounted on a 200 Pin FR4 substrate.
Synchronous design allows precise cycle control with
the use of system clock. Data I/O transactions are
possible on both edges and Burst Lenths allow the
same device to be useful for a variety of high bandwidth,
high performance memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change without notice.
NOTE: Consult factory for availability of:
• Lead-Free or RoHS Products
• Vendor source control options
• Industrial temperature option
Clock Speed
CL-tRCD-tRP
OPERATING FREQUENCIES
DDR333 @CL=2.5
166MHz
2.5-3-3
DDR266 @CL=2
133MHz
2-2-2
DDR266 @CL=2.5
133MHz
2.5-3-3
DDR200 @CL=2
100MHz
2-2-2
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2005
Rev. 1
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com




W3EG6433S-AD4 pdf, 반도체, 판매, 대치품
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Voltage on any pin relative to VSS
VIN, VOUT
Voltage on VCC supply relative to VSS
VCC, VCCQ
Storage Temperature
TSTG
Power Dissipation
PD
Short Circuit Current
IOS
Note:
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
W3EG6433S-AD4
-BD4
PRELIMINARY
Value
-0.5 to 3.6
-1.0 to 3.6
-55 to +150
8
50
Units
V
V
°C
W
mA
Parameter
Supply Voltage
Supply Voltage
Reference Voltage
Termination Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
DC CHARACTERISTICS
0°C TA 70°C, VCC = 2.5V ± 0.2V
Symbol
VCC
VCCQ
VREF
VTT
VIH
VIL
VOH
VOL
Min
2.3
2.3
VCCQ/2 - 50mV
VREF - 0.04
VREF + 0.15
-0.3
VTT + 0.76
Max
2.7
2.7
VCCQ/2 + 50mV
VREF + 0.04
VCCQ + 0.3
VREF - 0.15
VTT - 0.76
Unit
V
V
V
V
V
V
V
V
CAPACITANCE
TA = 25°C, f = 1MHz, VCC = 3.3V, VREF =1.4V ± 200mV
Parameter
Symbol
Input Capacitance (A0-A12)
Input Capacitance (RAS#, CAS#, WE#)
Input Capacitance (CKE0)
Input Capacitance (CK0,CK0#)
Input Capacitance (CS0#)
Input Capacitance (DQM0-DQM8)
Input Capacitance (BA0-BA1)
Data input/output capacitance (DQ0-DQ63)(DQS)
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIN7
COUT
Max
29
29
29
5.5
29
8
29
8
Unit
pF
pF
pF
pF
pF
pF
pF
pF
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2005
Rev. 1
4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

4페이지










W3EG6433S-AD4 전자부품, 판매, 대치품
White Electronic Designs
W3EG6433S-AD4
-BD4
PRELIMINARY
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC
OPERATING CONDITIONS
AC CHARACTERISTICS
335
262
265/202
UNITS NOTES
PARAMETER
SYMBOL MIN MAX MIN MAX MIN MAX
Access window of DQs from CK/CK#
tAC -0.70 +0.70 -0.75 +0.75 -0.75 +0.75 ns
CK high-level width
tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK
26
CK low-level width
tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK
26
Clock cycle time
CL = 2.5 tCK (2.5)
6
13 7.5 13 7.5 13 ns 40, 45
CL = 2 tCK (2)
7.5
13
7.5
13 7.5/10 13
ns 40, 45
DQ and DM input hold time relative to DQS
tDH 0.45
0.5
0.5
ns 23, 27
DQ and DM input setup time relative to DQS
tDS 0.45
0.5
0.5
ns 23, 27
DQ and DM input pulse width (for each input)
tDIPW 1.75 1.75 1.75
ns 27
Access window of DQS from CK/CK#
tDQSCK -0.60 +0.60 -0.75 +0.75 -0.75 +0.75 ns
DQS input high pulse width
tDQSH 0.35 0.35 0.35
tCK
DQS input low pulse width
tDQSL 0.35 0.35 0.35
tCK
DQS-DQ skew, DQS to last DQ valid, per group, per access
tDQSQ
0.4
0.5
0.5 ns 22, 23
Write command to first DQS latching transition
tDQSS 0.75 1.25 0.75 1.25 0.75 1.25
tCK
DQS falling edge to CK rising - setup time
tDSS 0.20 0.20 0.20
tCK
DQS falling edge from CK rising - hold time
tDSH 0.20 0.20 0.20
tCK
Half clock period
tHP tCH,tCL
tCH,tCL
tCH,tCL
ns 8
Data-out high-impedance window from CK/CK#
tHZ
+0.70
+0.75
+0.75 ns 16, 37
Data-out low-impedance window from CK/CK#
tLZ -0.70 -0.75 -0.75
ns 16, 37
Address and control input hold time (fast slew rate)
tIHF 0.75 0.90 0.90
ns 12
Address and control input setup time (fast slew rate)
tISF 0.75 0.90 .900
ns 12
Address and control input hold time (slow slew rate)
tIHS 0.8
1
1 ns 12
Address and control input setup time (slow slew rate)
tISS 0.8
1
1 ns 12
Address and Control input pulse width (for each input)
tIPW 2.2
2.2
2.2
ns
LOAD MODE REGISTER command cycle time
tMRD 12 15 15 ns
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2005
Rev. 1
7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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W3EG6433S-AD4

256MB - 32Mx64 DDR SDRAM UNBUFFERED

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