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부품번호 | W3EG72126S-JD3 기능 |
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기능 | 1GB-128Mx72 DDR SDRAM REGISTERED ECC | ||
제조업체 | White Electronic | ||
로고 | |||
White Electronic Designs
W3EG72126S-D3
-JD3
-AJD3
PRELIMINARY*
1GB-128Mx72 DDR SDRAM REGISTERED ECC w/PLL
FEATURES
Double-data-rate architecture
DDR200, DDR266 and DDR333:
• JEDEC design specifications
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input.
Auto and self refresh
Serial presence detect
Power supply: VCC = 2.5V ± 0.20V
JEDEC standard 184 pin DIMM package
• Package height options:
www.DataSheet4U.com JD3: 30.48mm (1.20") and
AJD3: 28.70mm (1.13")
• Consult factory for availability of lead-free
products.
DESCRIPTION
The W3EG72126S is a 128Mx72 Double Data Rate
SDRAM memory module based on 512Mb DDR SDRAM
components. The module consists of eighteen 128Mx4
DDR SDRAMs in 66 pin TSOP packages mounted on a
184 pin FR4 substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change without notice.
Clock Speed
CL-tRCD-tRP
DDR333 @CL=2.5
166MHz
2.5-3-3
OPERATING FREQUENCIES
DDR266 @CL=2
133MHz
2-2-2
DDR266 @CL=2
133MHz
2-3-3
DDR266 @CL=2.5
133MHz
2.5-3-3
DDR200 @CL=2
100MHz
2-2-2
November 2004
Rev. 3
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to VSS
Voltage on VCC supply relative to VSS
Storage Temperature
Power Dissipation
Short Circuit Current
Symbol
VIN, VOUT
VCC, VCCQ
TSTG
PD
IOS
Note:
Permanent device damage may occur if ‘ABSOLUTE MAXIMUM RATINGS’ are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability
W3EG72126S-D3
-JD3
-AJD3
PRELIMINARY
Value
-0.5 to 3.6
-1.0 to 3.6
-55 to +150
27
50
Units
V
V
°C
W
mA
Parameter
Supply Voltage
Supply Voltage
Reference Voltage
Termination Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
DC CHARACTERISTICS
0°C ≤ TA ≤ 70°C, VCC = 2.5V ± 0.2V
Symbol
Min
VCC
VCCQ
VREF
VTT
VIH
VIL
VOH
VOL
2.3
2.3
1.15
1.15
VREF + 0.15
-0.3
VTT + 0.76
—
Max
2.7
2.7
1.35
1.35
VCCQ + 0.3
VREF -0.15
—
VTT-0.76
Unit
V
V
V
V
V
V
V
V
Parameter
Input Capacitance (A0-A12)
Input Capacitance (RAS#,CAS#,WE#)
Input Capacitance (CKE0)
Input Capacitance (CK0#,CK0)
Input Capacitance (CS0#)
Input Capacitance (DQM0-DQM8)
Input Capacitance (BA0-BA1)
Data input/output capacitance (DQ0-DQ63)(DQS)
Data input/output capacitance (CB0-CB7)
CAPACITANCE
TA = 25°C. f = 1MHz, VCC = 2.5V ± 0.2V
Symbol
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIN7
COUT
COUT
Max Unit
6.25 pF
6.25 pF
6.25 pF
5.5 pF
6.25 pF
8 pF
6.25 pF
8 pF
8 pF
November 2004
Rev. 3
4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
4페이지 White Electronic Designs
W3EG72126S-D3
-JD3
-AJD3
PRELIMINARY
DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A
IDD1 : OPERATING CURRENT : ONE BANK
IDD7A : OPERATING CURRENT : FOUR BANKS
1. Typical Case : VCC=2.5V, T=25°C
2. Worst Case : VCC=2.7V, T=10°C
3. Only one bank is accessed with tRC (min), Burst
Mode, Address and Control inputs on NOP edge
are changing once per clock cycle. IOUT = 0mA
4. Timing Patterns :
• DDR200 (100 MHz, CL=2) : tCK=10ns, CL2,
BL=4, tRCD=2*tCK, tRAS=5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the
same timing with random address changing;
50% of data changing at every burst
• DDR266 (133MHz, CL=2.5) : tCK=7.5ns,
CL=2.5, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
• DDR266 (133MHz, CL=2) : tCK=7.5ns, CL=2,
BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
• DDR333 (166MHz, CL=2.5) : tCK=6ns, BL=4,
tRCD=10*tCK, tRAS=7*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
1. Typical Case : VCC=2.5V, T=25°C
2. Worst Case : VCC=2.7V, T=10°C
3. Four banks are being interleaved with tRC (min),
Burst Mode, Address and Control inputs on NOP
edge are not changing. Iout=0mA
4. Timing Patterns :
• DDR200 (100 MHz, CL=2) : tCK=10ns, CL2,
BL=4, tRRD=2*tCK, tRCD=3*tCK, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0
- repeat the same timing with random address
changing; 100% of data changing at every
burst
• DDR266 (133MHz, CL=2.5) : tCK=7.5ns,
CL=2.5, BL=4, tRRD=3*tCK, tRCD=3*tCK
Read with Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
• DDR266 (133MHz, CL=2) : tCK=7.5ns, CL2=2,
BL=4, tRRD=2*tCK, tRCD=2*tCK
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
• DDR333 (166MHz, CL=2.5) : tCK=6ns,
BL=4, tRRD=3*tCK, tRCD=3*tCK, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
Legend:
A = Activate, R = Read, W = Write, P = Precharge, N = NOP
A (0-3) = Activate Bank 0-3
R (0-3) = Read Bank 0-3
November 2004
Rev. 3
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
7페이지 | |||
구 성 | 총 15 페이지수 | ||
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W3EG72126S-JD3 | 1GB-128Mx72 DDR SDRAM REGISTERED ECC | White Electronic |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |