|
|
|
부품번호 | W3EG7234S-D3 기능 |
|
|
기능 | 256MB - 32Mx72 DDR SDRAM REGISTERED | ||
제조업체 | White Electronic | ||
로고 | |||
White Electronic Designs
W3EG7234S-D3
-JD3
-AJD3
PRELIMINARY*
256MB - 32Mx72 DDR SDRAM REGISTERED, w/PLL
FEATURES
Double-data-rate architecture
Clock speeds: 100MHz and 133MHz
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2,5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh
Serial presence detect
Power Supply: 2.5V ± 0.20V
JEDEC standard 184 pin DIMM package
•
www.DataSheet4U.com
Package height options:
JD3: 30.48mm (1.20")
AJD3: 28.70mm (1.13")
DESCRIPTION
The W3EG7234S is a 32Mx72 Double Data Rate
SDRAM memory module based on 128Mb DDR
SDRAM component. The module consists of eighteen
32Mx4 DDR SDRAMs in 66 pin TSOP package
mounted on a 184 Pin FR4 substrate.
Synchronous design allows precise cycle control with
the use of system clock. Data I/O transactions are
possible on both edges and Burst Lenths allow the
same device to be useful for a variety of high bandwidth,
high performance memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change without notice.
Clock Speed
CL-tRCD-tRP
OPERATING FREQUENCIES
DDR266 @CL=2
133MHz
2-2-2
DDR266 @CL=2.5
133MHz
2.5-3-3
DDR200 @CL=2
100MHz
2-2-2
December 2004
Rev. 2
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
W3EG7234S-D3
-JD3
-AJD3
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to VSS
Voltage on VCC supply relative to VSS
Storage Temperature
Power Dissipation
Short Circuit Current
Symbol
VIN, VOUT
VCC, VCCQ
TSTG
PD
IOS
Note:
Permanent device damage may occur if ‘ABSOLUTE MAXIMUM RATINGS’ are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability
Value
-0.5 to 3.6
-1.0 to 3.6
-55 to +150
27
50
Units
V
V
°C
W
mA
Parameter
Supply Voltage
Supply Voltage
Reference Voltage
Termination Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
DC CHARACTERISTICS
0°C ≤ TA ≤ 70°C, VCC = 2.5V ± 0.2V
Symbol
Min
VCC
VCCQ
VREF
VTT
VIH
VIL
VOH
VOL
2.3
2.3
1.15
1.15
VREF + 0.15
-0.3
VTT + 0.76
—
Max
2.7
2.7
1.35
1.35
VCCQ + 0.3
VREF -0.15
—
VTT-0.76
Unit
V
V
V
V
V
V
V
V
Parameter
Input Capacitance (A0-A12)
Input Capacitance (RAS#,CAS#,WE#)
Input Capacitance (CKE0)
Input Capacitance (CK0#,CK0)
Input Capacitance (CS0#)
Input Capacitance (DQS0-DQS17)
Input Capacitance (BA0-BA1)
Data input/output capacitance (DQ0-DQ63)(DQS)
Data input/output capacitance (CB0-CB7)
CAPACITANCE
TA = 25°C. f = 1MHz, VCC = 2.5V
Symbol
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIN7
COUT
COUT
Max
6.25
6.25
6.25
5.5
6.25
13
6.25
13
13
Unit
pF
pF
pF
pF
pF
pF
pF
pF
pF
December 2004
Rev. 2
4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
4페이지 White Electronic Designs
W3EG7234S-D3
-JD3
-AJD3
PRELIMINARY
DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A
IDD1 : OPERATING CURRENT: ONE BANK
1. Typical Case: VCC = 2.5V, T = 25°C
2. Worst Case: VCC = 2.7V, T = 10°C
3. Only one bank is accessed with tRC (min), Burst
Mode, Address and Control inputs on NOP edge are
changing once per clock cycle. lOUT = 0mA
4. Timing patterns
• DDR200 (100MHz, CL = 2) : tCK = 10ns, CL2, BL =
4, tRCD = 2*tCK, tRAg = 5*tCK
Read: A0 N R0 N N P0 N A0 N - repeat the same
timing with random address changing; 50% of data
changing at every burst
• DDR266 (133MHz, CL = 2.5) : tCK = 7.5ns, CL =
2.5, BL = 4, tRCD = 3*tCK, tRC = 9*tCK, tRAg = 5*tCK
Read: A0 N N R0 N P0 N N N A0 N - repeat the
same timing with random address changing; 50% of
data changing at every burst
• DDR266 (133MHz, CL = 2) : tCK = 7.5ns, CL = 2, BL
= 4, tRCD = 3*tCK, tRC = 9*tCK, tRAg = 5*tCK
Read: A0 N N R0 N P0 N N N A0 N - repeat the
same timing with random address changing; 50% of
data changing at every burst
IDD7A: OPERATING CURRENT: FOUR BANKS
1. Typical Case: VCC = 2.5V, T = 25°C
2. Worst Case: VCC = 2.7V, T = 10°C
3. Four banks are being interleaved with tRC (min), Burst
Mode, Address and Control inputs on NOP edge are
not changing.
lout = 0mA
4. Timing patterns
• DDR200 (100MHz, CL = 2) : tCK = 10ns, CL2,
BL = 4, tRRD = 2*tCK, tRCD = 3*tCK, Read with
autoprecharge
Read: A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0
- repeat the same timing with random address
changing; 100% of data changing at every burst
• DDR266 (133MHz, CL = 2.5) : tCK = 7.5ns, CL =
2.5, BL = 4, tRRD = 3*tCK, tRCD = 3*tCK Read with
autoprecharge
Read: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1
R0 - repeat the same timing with random address
changing; 100% of data changing at every burst
• DDR266 (133MHz, CL = 2): tCK = 7.5ns, CL2 = 2,
BL = 4, tRRD = 2*tCK, tRCD = 3*tCK
Read: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1
R0 - repeat the same timing with random address
changing; 100% of data changing at every burst
Legend: A = Activate, R = Read, W = Write, P = Precharge, N = NOP
A (0-3) = Activate Bank 0-3
R (0-3) = Read Bank 0-3
December 2004
Rev. 2
7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
7페이지 | |||
구 성 | 총 14 페이지수 | ||
다운로드 | [ W3EG7234S-D3.PDF 데이터시트 ] |
당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는 |
구매 문의 | 일반 IC 문의 : 샘플 및 소량 구매 ----------------------------------------------------------------------- IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한 광범위한 전력 반도체를 판매합니다. 전력 반도체 전문업체 상호 : 아이지 인터내셔날 사이트 방문 : [ 홈페이지 ] [ 블로그 1 ] [ 블로그 2 ] |
부품번호 | 상세설명 및 기능 | 제조사 |
W3EG7234S-D3 | 256MB - 32Mx72 DDR SDRAM REGISTERED | White Electronic |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |