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What is W3EG7264S-D3?

This electronic component, produced by the manufacturer "White Electronic", performs the same function as "512MB - 64Mx72 DDR SDRAM UNBUFFERED".


W3EG7264S-D3 Datasheet PDF - White Electronic

Part Number W3EG7264S-D3
Description 512MB - 64Mx72 DDR SDRAM UNBUFFERED
Manufacturers White Electronic 
Logo White Electronic Logo 


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White Electronic Designs
W3EG7264S-JD3-D3
PRELIMINARY*
512MB – 64Mx72 DDR SDRAM UNBUFFERED
FEATURES
Double-data-rate architecture
DDR200, DDR266, DDR333 and DDR400
• JEDEC design specifications
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input.
Auto and self refresh
Serial presence detect
Power supply: DDR333, 266, 200: VCC = VCCQ =
+2.5V ± 0.2V; DDR400: VCC = VCCQ = +2.6V ± 0.1V
JEDECwww.DataSheet4U.com standard 184 pin DIMM package
• PCB Height: 30.48mm (1.20") Max
DESCRIPTION
The W3EG7264S is a 64Mx72 Double Data Rate
SDRAM memory module based on 512Mb DDR SDRAM
components. The module consists of nine 64Mx8 DDR
SDRAMs in 66 pin TSOP packages mounted on a 184
pin FR4 substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change without notice.
NOTE: Consult Factory for availability of:
* Lead-Free Products
* Vendor source control options
* Industrial Temperature option
Clock Speed
CL-tRCD-tRP
DDR400 @CL=3
200MHz
3-3-3
OPERATING FREQUENCIES
DDR333 @CL=2.5
166MHz
2.5-3-3
DDR266 @CL=2
133MHz
2-2-2
DDR266 @CL=2.5
133MHz
2.5-3-3
DDR200 @CL=2
100MHz
2-2-2
May 2005
Rev. 5
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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W3EG7264S-D3 equivalent
White Electronic Designs
W3EG7264S-JD3-D3
PRELIMINARY
IDD SPECIFICATIONS AND TEST CONDITIONS
DDR333, 266, 200: VCC = VCCQ = +2.5V ± 0.2V; DDR400: VCC = VCCQ = +2.6V ± 0.1V
Includes DDR SDRAM component only
Parameter
Symbol Conditions
Operating Current
IDD0 One device bank; Active - Precharge;
tRC=tRC (MIN); tCK=tCK (MIN); DQ,DM
and DQS inputs changing once per
clock cycle; Address and control
inputs changing once every two
cycles.
Operating Current
IDD1 One device bank; Active-Read-
Precharge Burst = 2; tRC=tRC (MIN);
tCK=tCK (MIN); lOUT = 0mA; Address
and control inputs changing once per
clock cycle.
Precharge Power-
IDD2P All device banks idle; Power-down
Down Standby Current
mode; tCK=tCK (MIN); CKE=(low)
Idle Standby Current
IDD2F CS# = High; All device banks idle;
tCK=tCK (MIN); CKE = high; Address
and other control inputs changing
once per clock cycle. VIN = VREF for
DQ, DQS and DM.
Active Power-Down
Standby Current
IDD3P One device bank active; Power-
Down mode; tCK (MIN); CKE=(low)
Active Standby Current IDD3N CS# = High; CKE = High; One device
bank; Active-Precharge; tRC=tRAS
(MAX); tCK=tCK (MIN); DQ, DM and
DQS inputs changing twice per clock
cycle; Address and other control
inputs changing once per clock cycle.
Operating Current
IDD4R Burst = 2; Reads; Continuous burst;
One device bank active; Address
and control inputs changing once
per clock cycle; TCK= TCK (MIN); lOUT
= 0mA.
Operating Current
IDD4W Burst = 2; Writes; Continuous burst;
One device bank active; Address
and control inputs changing once per
clock cycle; tCK=tCK (MIN); DQ,DM
and DQS inputs changing once per
clock cycle.
Auto Refresh Current IDD5 tRC = tRC (MIN)
Self Refresh Current
IDD6 CKE 0.2V
Operating Current
IDD7A Four bank interleaving Reads (BL=4)
with auto precharge with tRC=tRC
(MIN); tCK=tCK (MIN); Address and
control inputs change only during
Active Read or Write commands.
DDR400@
CL=3
Max
1395
1665
45
495
405
540
1710
1758
3105
45
4050
DDR333@
CL=2.5
Max
1170
1440
45
405
315
450
1485
1575
2610
45
3645
DDR266@
CL=2
Max
1170
1440
45
405
315
450
1485
1575
2610
45
3645
DDR266@
CL=2.5
Max
1170
1440
45
405
315
450
1485
1575
2610
45
3645
DDR200@
CL=2
Max Units
1170 mA
1440 mA
45 rnA
405 mA
315 mA
450 mA
1485 mA
1575 rnA
2610 mA
45 mA
3645 mA
May 2005
Rev. 5
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com


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Featured Datasheets

Part NumberDescriptionMFRS
W3EG7264S-D3The function is 512MB - 64Mx72 DDR SDRAM UNBUFFERED. White ElectronicWhite Electronic

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