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W3EG7264S-JD3 데이터시트 PDF




White Electronic에서 제조한 전자 부품 W3EG7264S-JD3은 전자 산업 및 응용 분야에서
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부품번호 W3EG7264S-JD3 기능
기능 512MB - 64Mx72 DDR SDRAM UNBUFFERED
제조업체 White Electronic
로고 White Electronic 로고


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W3EG7264S-JD3 데이터시트, 핀배열, 회로
White Electronic Designs
W3EG7264S-JD3-D3
PRELIMINARY*
512MB – 64Mx72 DDR SDRAM UNBUFFERED
FEATURES
Double-data-rate architecture
DDR200, DDR266, DDR333 and DDR400
• JEDEC design specifications
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input.
Auto and self refresh
Serial presence detect
Power supply: DDR333, 266, 200: VCC = VCCQ =
+2.5V ± 0.2V; DDR400: VCC = VCCQ = +2.6V ± 0.1V
JEDECwww.DataSheet4U.com standard 184 pin DIMM package
• PCB Height: 30.48mm (1.20") Max
DESCRIPTION
The W3EG7264S is a 64Mx72 Double Data Rate
SDRAM memory module based on 512Mb DDR SDRAM
components. The module consists of nine 64Mx8 DDR
SDRAMs in 66 pin TSOP packages mounted on a 184
pin FR4 substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change without notice.
NOTE: Consult Factory for availability of:
* Lead-Free Products
* Vendor source control options
* Industrial Temperature option
Clock Speed
CL-tRCD-tRP
DDR400 @CL=3
200MHz
3-3-3
OPERATING FREQUENCIES
DDR333 @CL=2.5
166MHz
2.5-3-3
DDR266 @CL=2
133MHz
2-2-2
DDR266 @CL=2.5
133MHz
2.5-3-3
DDR200 @CL=2
100MHz
2-2-2
May 2005
Rev. 5
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com




W3EG7264S-JD3 pdf, 반도체, 판매, 대치품
White Electronic Designs
W3EG7264S-JD3-D3
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to VSS
Voltage on VCC supply relative to VSS
Storage Temperature
Power Dissipation
Short Circuit Current
Symbol
VIN, VOUT
VCC, VCCQ
TSTG
PD
IOS
Note:
Permanent device damage may occur if ‘ABSOLUTE MAXIMUM RATINGS’ are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability
Value
-0.5 to 3.6
-1.0 to 3.6
-55 to +150
9
50
Units
V
V
°C
W
mA
Parameter
Supply Voltage
Supply Voltage
Reference Voltage
Termination Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
DC CHARACTERISTICS
0°C TA 70°C; DDR333, 266, 200: VCC = VCCQ = +2.5V ± 0.2V; DDR400: VCC = VCCQ = +2.6V ± 0.1V
Symbol
Min Max
VCC
VCCQ
VREF
VTT
VIH
VIL
VOH
VOL
2.3
2.3
1.15
1.15
VREF + 0.15
-0.3
VTT + 0.76
2.7
2.7
1.35
1.35
VCCQ + 0.3
VREF -0.15
VTT-0.76
Unit
V
V
V
V
V
V
V
V
CAPACITANCE
TA = 25°C. f = 1MHz; DDR333, 266, 200: VCC = VCCQ = +2.5V ± 0.2V; DDR400: VCC = VCCQ = +2.6V ± 0.1V
Parameter
Symbol
Max
Input Capacitance (A0-A12)
Input Capacitance (RAS#,CAS#,WE#)
Input Capacitance (CKE0, CKE1)
Input Capacitance (CK0#,CK0)
Input Capacitance (CS0#, CS1#)
Input Capacitance (DQM0-DQM8)
Input Capacitance (BA0-BA1)
Data input/output capacitance (DQ0-DQ63)(DQS)
Data input/output capacitance (CB0-CB7)
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIN7
COUT
COUT
32
32
32
32
32
8
32
8
8
Unit
pF
pF
pF
pF
pF
pF
pF
pF
pF
May 2005
Rev. 5
4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

4페이지










W3EG7264S-JD3 전자부품, 판매, 대치품
White Electronic Designs
W3EG7264S-JD3-D3
PRELIMINARY
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS
DDR333, 266, 200: VCC = VCCQ = +2.5V ± 0.2V; DDR400: VCC = VCCQ = +2.6V ± 0.1V
AC Characteristics
403 335 262/265 202
Parameter
Symbol Min Max Min Max Min Max Min Max Units Notes
Access window of DQs from CK, CK#
tAC -0.70 +0.70 -0.70 +0.70 -0.75 +0.75 -0.75 +0.75 ns
CK high-level width
tCH 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK 16
CK low-level width
tCL 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK 16
Clock cycle time
CL=3 tCK (3) 5
7.5
ns 22
CL=2.5 tCK (2.5) 6 13 6 13 7.5 13 7.5 13 ns 22
CL=2 tCK (2) 7.5 13 7.5 13 7.5 13 10 13 ns 22
DQ and DM input hold time relative to DQS
tDH 0.45
0.40
0.5
0.5
ns 14,17
DQ and DM input setup time relative to DQS
tDS 0.45
0.40
0.5
0.5
ns 14,17
DQ and DM input pulse width (for each input) tDIPW 1.75 1.75 1.75 1.75
ns 17
Access window of DQS from CK, CK#
tDQSCK -0.60 +0.60 -0.60 +0.60 -0.75 +0.75 -0.75 +0.75 ns
DQS input high pulse width
tDQSH 0.35 0.35 0.35 0.35
tCK
DQS input low pulse width
tDQSL 0.35 0.35 0.35 0.35
tCK
DQS-DQ skew, DQS to last DQ valid, per group,
tDQSQ
0.40
0.45
per access
0.5
0.5 ns 13,14
Write command to first DQS latching transition
tDQSS 0.72 1.28 0.75 1.25 0.75 1.25 0.75 1.25 tCK
DQS falling edge to CK rising - setup time
tDSS 0.2 0.2 0.2 0.2 tCK
DQS falling edge from CK rising - hold time
tDSH 0.2 0.2 0.2 0.2 tCK
Half clock period
tHP tCH, tCL
tCH, tCL
tCH, tCL
tCH, tCL
ns 18
Data-out high-impedance window from CK, CK#
tHZ
+0.70
+0.70
+0.75
+0.75 ns 8,19
Data-out low-impedance window from CK, CK# tLZ -0.70 -0.70 -0.75 -0.75
ns 8,20
Address and control input hold time (fast slew rate)
tIHf 0.60
0.75
0.90
0.90
ns 6
Address and control input set-up time (fast slew rate)
tISf 0.60
0.75
0.90
0.90
ns 6
Address and control input hold time (slow slew rate)
tIHs 0.60
0.80
1
1
ns 6
Address and control input setup time (slow slew rate)
tISs 0.60
0.80
1
1
ns 6
Address and control input pulse width (for each input) tIPW 2.2 2.2 2.2 2.2 ns
LOAD MODE REGISTER command cycle time
tMRD 10
12
15
15
ns
DQ-DQS hold, DQS to first DQ to go non-valid, per
access
tQH tHP-tQHS
tHP-tQHS
tHP-tQHS
tHP-tQHS
ns 13,14
Data hold skew factor
ACTIVE to PRECHARGE command
ACTIVE to READ with Auto precharge command
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period
tQHS
tRAS
tRAP
tRC
tRFC
0.50 0.55 0.75 0.75 ns
40 70,000 42 70,000 40 120,000 45 120,000 ns
15 15 15 20 ns
55 60 60 65 ns
70 72 75 75 ns
15
21
May 2005
Rev. 5
7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

7페이지


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512MB - 64Mx72 DDR SDRAM UNBUFFERED

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