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W3EG7266S-AD4 데이터시트 PDF




White Electronic에서 제조한 전자 부품 W3EG7266S-AD4은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 W3EG7266S-AD4 기능
기능 512MB - 64Mx72 DDR SDRAM UNBUFFERED ECC
제조업체 White Electronic
로고 White Electronic 로고


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W3EG7266S-AD4 데이터시트, 핀배열, 회로
White Electronic Designs
W3EG7266S-AD4
-BD4
PRELIMINARY*
512MB – 64Mx72 DDR SDRAM UNBUFFERED ECC w/PLL
FEATURES
Double-data-rate architecture
DDR200, DDR266, DDR300 and DDR400
• JEDEC design specifications
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh
Serial presence detect
Power supply:
• VCC = VCCQ = +2.5V ± 0.2V (100, 133 and
166MHz)
www.DataSheet4U.com
• VCC = VCCQ = +2.6V ± 0.1V (200MHz)
JEDEC standard 200 pin SO-DIMM package
• Package height options:
AD4: 35.05 mm (1.38”)
BD4: 31.75 mm (1.25”)
DESCRIPTION
The W3EG7266S is a 64Mx72 Double Data Rate
SDRAM memory module based on 512Mb DDR SDRAM
components. The module consists of nine 64Mx8 DDR
SDRAMs in 66 pin TSOP packages mounted on a 200
pin FR4 substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible
on both edges and Burst Lengths allow the same device to
be useful for a variety of high bandwidth, high performance
memory system applications.
* This data sheet describes a product that is not fully qualified or characterized and is
subject to change without notice.
NOTE: Consult factory for availability of:
• Lead-Free Products
• Vendor source control options
• Industrial temperature options
Clock Speed
CL-tRCD-tRP
DDR400@CL=3
200MHz
3-3-3
OPERATING FREQUENCIES
DDR333@CL=2.5
166MHz
2.5-3-3
DDR266@CL=2
133MHz
2-2-2
DDR266@CL=2.5
133MHz
2.5-3-3
DDR200@CL=2
100MHz
2-2-2
October 2004
Rev. 7
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com




W3EG7266S-AD4 pdf, 반도체, 판매, 대치품
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Voltage on any pin relative to VSS
VIN, VOUT
Voltage on VCC supply relative to VSS
VCC, VCCQ
Storage Temperature
TSTG
Power Dissipation
PD
Short Circuit Current
IOS
Note:
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
W3EG7266S-AD4
-BD4
PRELIMINARY
Value
– 0.5 ~ 3.6
–1.0 ~ 3.6
– 55 ~ +150
9
50
Units
V
V
°C
W
mA
Parameter
Supply Voltage
Supply Voltage
Reference Voltage
Termination Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
DC CHARACTERISTICS
0°C TA 70°C, VCC = 2.5V ± 0.2V
Symbol
Min
VCC
VCCQ
VREF
VTT
VIH
VIL
VOH
VOL
2.3
2.3
1.15
1.15
VREF + 0.15
– 0.3
VTT + 0.76
Max
2.7
2.7
1.35
1.35
VCCQ + 0.3
VREF – 0.15
VTT – 0.76
Unit
V
V
V
V
V
V
V
V
Parameter
Input Capacitance (A0-A12)
Input Capacitance (RAS#,CAS#,WE#)
Input Capacitance (CKE0,CKE1)
Input Capacitance (CK0,CK0#)
Input Capacitance (CS0#,CS1#)
Input Capacitance (DQM0-DQM8)
Input Capacitance (BA0-BA1)
Data input/output Capacitance (DQ0-DQ63)(DQS)
Data input/output Capacitance (CB0-CB7)
October 2004
Rev. 7
CAPACITANCE
TA = 25°C, f = 1MHz, VCC = 2.5V ± 0.2V
Symbol
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIN7
COUT
COUT
Max
29
29
29
5.5
29
8
29
8
8
Unit
pF
pF
pF
pF
pF
pF
pF
pF
pF
4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

4페이지










W3EG7266S-AD4 전자부품, 판매, 대치품
White Electronic Designs
W3EG7266S-AD4
-BD4
PRELIMINARY
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS
DDR400: VCC = VCCQ = +2.6V ± 0.1V
AC CHARACTERISTICS
403 335 262 265 202
PARAMETER
Access window of DQs from CK/CK#
CK high-level width
CK low-level width
Clock cycle time
CL = 3
CL = 2.5
CL = 2
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per
access
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
Address and control input hold time (1 V/ns)
Address and control input setup time (1 V/ns)
Address and control input hold time (0.5 V/ns)
Address and control input setup time (0.5 V/ns)
Address and Control input pulse width (for each input)
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per
access
Data hold skew factor
ACTIVE to PRECHARGE command
ACTIVE to READ with Auto precharge command
ACTIVE to ACTIVE/AUTO REFRESH command
period
AUTO REFRESH command period
ACTIVE to READ or WRITE delay
PRECHARGE command period
DQS read preamble
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
DQS write preamble setup time
SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES
tAC -0.7 +0.7 -0.7 +0.7 -0.75 +0.75 -0.75 0.75 -0.8 0.8 ns
tCH 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK 25
tCL 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK 25
tCK (3) 5 7.5 6 13 7.5 13 7.5 13 8 13 ns 38, 43
tCK (2.5) 6 13 7.5 13 7.5 13 7.5/10 13 10 13 ns 38, 43
tCK (2) 7.5 13
ns 37, 42
tDH 0.4 0.45 0.5 0.6 ns 22, 26
tDS 0.4 0.45 0.5 0.6 ns 22, 26
tDIPW 1.75 1.75 1.75
2
ns 26
tDQSCK -0.6 +0.6 -0.60 +0.60 -0.75 +0.75 +0.75 -0.8 +0.8
ns
tDQSH 0.35 0.35 0.35
0.35
tCK
tDQSL 0.35 0.35 0.35
0.35
tCK
tDQSQ
0.40 0.45
0.5
0.5
0.6 ns 22
tDQSS
tDSS
tDSH
tHP
tHZ
tLZ
tIHF
tISF
tIHS
tISS
tIPW
tMRD
tQH
tQHS
tRAS
tRAP
tRC
0.72 1.28 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25
0.2 0.2 0.2 0.2 0.2
0.2 0.2 0.2 0.2 0.2
tCH,tCL
tCH,tCL
tCH,tCL
tCH,tCL
tCH,tCL
+0.70
+0.70
+0.75
+0.75
+0.8
-0.70 -0.70 -0.75 -0.75
-0.8
0.6 0.75 0.90 0.90 1.1 ns 12
0.6 0.75 0.90 0.90 1.1
0.6 0.80
1
1 1.1
0.6 0.80
1
1 1.1
2.20 2.2 2.2 2.2 2.2
2 12 15 15 16
tHP
- tQHS
tHP
- tQHS
tHP
- tQHS
tHP
- tQHS
tHP
- tQHS
0.50 0.60 0.75 0.75
1
40 70,000 42 70,000 40 120,000 40 120,000 40 120,000
15 15 15 20 20
55 60 60 65 70
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
29
16, 35
16, 35
12
12
12
12
22
30
tRFC 70 72 75 72 75
tRCD 15 15 15 20 20
tRP 15 15 15 20 20
tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1
tRPST 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6
tRRD 10 12 15 15 15
tWPRE 0.25 0.25 0.25 0.25 0.25
tWPRES
0
0
0
0
0
ns 41
ns
ns
tCK 36
tCK 36
ns
tCK
ns 17, 19
October 2004
Rev. 7
7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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부품번호상세설명 및 기능제조사
W3EG7266S-AD4

512MB - 64Mx72 DDR SDRAM UNBUFFERED ECC

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