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부품번호 MCZ33999 기능
기능 16-Output Switch
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MCZ33999 데이터시트, 핀배열, 회로
Freescale Semiconductor
Advance Information
Document Number: MC33999
Rev. 4.0, 4/2007
16-Output Switch with SPI
and PWM Control
33999
The 33999 is a 16-output low-side switch with a 24-bit serial input
control. It is designed for a variety of applications including inductive,
incandescent, and LED loads. The Serial Peripheral Interface (SPI)
provides both input control and diagnostic readout. Eight parallel inputs
are also provided for direct Pulse Width Modulation (PWM) control of
eight dedicated outputs. Additionally, an output-programmable PWM
input provides PWM of any combination of outputs. A dedicated reset
input provides the ability to clear all internal registers and turn all
outputs off.
The 33999 directly interfaces with microcontrollers and is
compatible with both 3.3 V and 5.0 V CMOS logic levels. The 33999,
in effect, serves as a bus expander and buffer with fault management
features that reduces the MCU’s fault management burden.
POWER DUAL OCTAL SERIAL SWITCH WITH
SERIAL PERIPHERAL INTERFACE I/O
EK SUFFIX (PB-FREE)
98ASA10506D
54-PIN SOICW EXPOSED PAD
Features
• Designed to Operate 5.0 V < VPWR < 27 V
• 24-Bit SPI for Control and Fault reporting, 3.3 V/5.0 V Compatible
• Outputs Are Current Limited (0.9 A to 2.5 A) to Drive
Incandescent Lamps
• Output Voltage Clamp of +50 V During Inductive Switching
• On/Off Control of Open Load Detect Current (LED Application)
ORDERING INFORMATION
Device
Temperature
Range (TA)
Package
MC33999EK/R2
MCZ33999EK/R2
-40°C to 125°C
54 SOICW-EP
www.DataSheet4U.com
• VPWR Standby Current < 10 µA
• RDS(ON) of 0.55 at 25°C Typical
• Independent Overtemperature Protection
• Output Selectable for PWM Control
• Output ON Short-to-VBAT and OFF Short-to-Ground/Open Detection
• 54-Pin Exposed Pad Package for Thermal Performance
• Pb-Free Packaging Designated by Suffix Code EK
3.3 V/5.0 V
33999
VPWR
VBAT
VDD
MCU
SCLK
CS
MISO
MOSI
PWM
RST
SOPWR VPWR
SCLK
CS
SI
SO
PWM
RST
PWM0
PWM1
PWM6
PWM7
PWM8
PWM9
PWM14
PWM15
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
GND
Solenoid/Relay
LED
Lamp
Figure 1. 33999 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2007. All rights reserved.




MCZ33999 pdf, 반도체, 판매, 대치품
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
ELECTRICAL RATINGS
VPWR Supply Voltage (1)
SPI Interface Logic Supply Voltage (1)
SPI Interface Logic Input Voltage (CS, PWM, SI, SO, SCLK, RST, PWMn) (1)
Output Drain Voltage
Frequency of SPI Operation (2)
Output Clamp Energy (3)
ESD Voltage (4)
Human Body Model
Machine Model
THERMAL RATINGS
Operating Temperature
Ambient
Junction
Case
Storage Temperature
Power Dissipation (TA = 25°C) (5)
Peak Package Reflow Temperature During Reflow (6), (7)
Thermal Resistance
Junction-to-Ambient (8)
Junction- to-Lead (9)
Junction-to-Flag
VPWR
SOPWR
VIN
VDS
fSPI
ECLAMP
VESD1
VESD2
TA
TJ
TC
TSTG
PD
TPPRT
RθJA
RθJL
RθJC
-1.5 to 50
-0.3 to 7.0
-0.3 to 7.0
-0.3 to 45
6.0
50
±2000
±200
-40 to 125
-40 to 150
-40 to 125
-55 to 150
1.7
Note 7
75
8.0
1.2
V
V
V
V
MHz
mJ
V
°C
°C
W
°C
°C/W
Notes
1. Exceeding these limits may cause malfunction or permanent damage to the device.
2. This parameter is guaranteed by design but not production tested.
3. Maximum output clamp energy capability at 150°C junction temperature using single non-repetitive pulse method.
4. ESD data is available upon request. ESD testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500
) and the Machine Model (CZAP = 200 pF, RZAP = 0 ).
5. Maximum power dissipation with no heat sink used.
6. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
7. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL),
Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.
MC33xxxD enter 33xxx), and review parametrics.
8. Tested per JEDEC test JESD52-2 (single-layer PWB).
9. Tested per JEDEC test JESD51-8 (two-layer PWB).
33999
4
Analog Integrated Circuit Device Data
Freescale Semiconductor

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MCZ33999 전자부품, 판매, 대치품
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 3.1 V SOPWR 5.25 V, 9.0 V VPWR 16 V, -40°C TC 125°C unless otherwise
noted. Typical values noted reflect the approximate parameter means at VPWR = 13 V, TA = 25°C under nominal conditions
unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max Unit
POWER OUTPUT TIMING
Output Slew Rate
RL = 60 (15)
Output Turn ON Delay Time (16)
Output Turn OFF Delay Time (16)
Output ON Short Fault Disable Report Delay (17)
Output OFF Open Fault Delay Time (17)
Output PWM Frequency
DIGITAL INTERFACE TIMING (23)
SR V/µs
1.0 2.0 10
T DLY(ON)
1.0
2.0
10
µs
T DLY(OFF)
1.0
4.0
10
µs
T DLY(SHORT) 100 – 450 µs
T DLY(OPEN)
100
450 µs
T FREQ
– 2.0 kHz
Required Low State Duration on VPWR for Reset
VPWR 0.2 V (18)
T RST
µs
– 10
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)
T LEAD
100
– ns
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)
T LAG
50
– ns
SI to Falling Edge of SCLK (Required Setup Time)
TSI (SU)
16
– ns
Falling Edge of SCLK to SI (Required Setup Time)
SI, CS, SCLK Signal Rise Time (19)
SI, CS, SCLK Signal Fall Time (19)
Time from Falling Edge of CS to SO Low Impedance (20)
Time from Rising Edge of CS to SO High Impedance (21)
Time from Rising Edge of SCLK to SO Data Valid (22)
TSI (HOLD)
20
– ns
TR(SI) – 5.0 – ns
TF(SI) – 5.0 – ns
T SO (EN)
– 50 ns
T SO (DIS)
– 50 ns
T VALID
25 80 ns
Notes
15. Output slew rate measured across a 60 resistive load.
16. Output turn ON and OFF delay time measured from 50% rising edge of CS to 80% and 20% of initial voltage.
17. Duration of fault before fault bit is set. Duration between access times must be greater than 450 µs to read faults.
18. This parameter is guaranteed by design but is not production tested.
19. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
20. Time required for valid output status data to be available on SO pin.
21. Time required for output status data to be terminated at SO pin.
22. Time required to obtain valid data out from SO following the rise of SCLK with 200 pF load.
23. This parameter is guaranteed by design. Production test equipment used 4.16 MHz, 5.5 V/3.1 V SPI Interface.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33999
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