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PDF PIP3106-D Data sheet ( Hoja de datos )

Número de pieza PIP3106-D
Descripción LOGIC LEVEL TOPFET
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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Philips Semiconductors
Logic level TOPFET
Product specification
PIP3106-D
DESCRIPTION
Monolithic temperature and
overload protected logic level power
MOSFET in TOPFET2 technology
assembled in a 3 pin surface mount
plastic package.
APPLICATIONS
General purpose switch for driving
lamps
motors
solenoids
heaters
QUICK REFERENCE DATA
SYMBOL PARAMETER
VDS
ID
PD
Tj
RDS(ON)
Continuous drain source voltage
Continuous drain current
Total power dissipation
Continuous junction temperature
Drain-source on-state resistance
IISL
Input supply current
VIS = 5 V
FEATURES
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TrenchMOS output stage
Current limiting
Overload protection
Overtemperature protection
Protection latched reset by input
5 V logic compatible input level
Control of output stage and
supply of overload protection
circuits derived from input
Low operating input current
permits direct drive by
micro-controller
ESD protection on all pins
Overvoltage clamping for turn
off of inductive loads
FUNCTIONAL BLOCK DIAGRAM
INPUT
O/V
CLAMP
RIG
LOGIC AND
PROTECTION
MAX.
50
8
40
150
100
650
UNIT
V
A
W
˚C
m
µA
DRAIN
POWER
MOSFET
PINNING - SOT428
PIN DESCRIPTION
1 input
2 drain
3 source
tab drain
SOURCE
Fig.1. Elements of the TOPFET.
PIN CONFIGURATION
tab
SYMBOL
D
TOPFET
2
13
I
P
S
October 2001
1
Rev 1.000

1 page




PIP3106-D pdf
Philips Semiconductors
Logic level TOPFET
MECHANICAL DATA
Plastic single-ended surface mounted package (Philips version of D-PAK); 3 leads
(one lead cropped)
Product specification
PIP3106-D
SOT428
seating plane
y
A
EA
A2
b2 A1
mounting
base
D
HE
L2
2
1
L
3
b1
e
b wM A
e1
L1
c
E1
D1
0 10 20 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1(1)
A2
b
b1
max.
b2
c
mm 2.38 0.65 0.89 0.89 1.1 5.36 0.4
2.22 0.45 0.71 0.71 0.9 5.26 0.2
D D1 E E1
max. max. max. min.
e
e1
HE
max.
L
6.22 4.81 6.73
5.98 4.45 6.47
4.0
2.285 4.57
10.4
9.6
2.95
2.55
L1
min.
0.5
L2
0.7
0.5
Note
1. Measured from heatsink back to lead.
OUTLINE
VERSION
IEC
REFERENCES
JEDEC
EIAJ
EUROPEAN
PROJECTION
w
y
max.
0.2 0.2
ISSUE DATE
SOT428
98-04-07
Fig.2. SOT428 surface mounting package1, centre pin connected to mounting base.
1 Epoxy meets UL94 V0 at 1/8". Net mass: 1.1 g
For soldering guidelines and SMD footprint design, please refer to Data Handbook SC18.
October 2001
5
Rev 1.000

5 Page










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