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PDF WT62P2 Data sheet ( Hoja de datos )
| Número de pieza | WT62P2 | |
| Descripción | Micro-controllers For Monitors Embedded Usb Function | |
| Fabricantes | Weltrend Semiconductor | |
| Logotipo |  |
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Weltrend Semiconductor, Inc.
WT62P2
Digital Monitor Controller with USB Function
(Flash Memory Type)
www.DataSheet4U.com
Preliminary Data Sheet
REV. 1.04
Sep. 20, 2001
The information in this document is subject to change without notice.
©Weltrend Semiconductor, Inc. All Rights Reserved.
2F, No. 24, Industry E. 9th RD., Science-Based Industrial Park, Hsin-Chu, Taiwan
TEL:886-3-5780241 FAX:886-3-5794278.5770419
Email:[email protected]
1 page  
WT62P2 v1.04
USB Monitor Controller
42 43 41 40 VIN
43 - - - NC
44 44 42 - D-
I Vsync input.
No Connection.
I/O USB D- signal.
FUNCTIONAL DESCRIPTION
CPU
8-bit 6502 compatible CPU with 16-bit address bus and 8-bit data bus operates at 6MHz. The
non-maskable interrupt (/NMI) of 6502 is modified to be maskable and is defined as INT0 with higher
priority. The interrupt request (/IRQ) of 6502 is defined as INT1 with lower priority.
Please refer the 6502 reference menu for more detail.
RAM
The 1024 bytes SRAM include :
128 bytes SRAM are from $0080H to $00FFH
256 bytes SRAM are from $0100H to $01FFH
256 bytes SRAM are from $0200H to $02FFH
256 bytes SRAM are from $0300H to $03FFH
128 bytes SRAM are from $0400H to $047FH
The 256 bits bit-addressable SRAM are from $0500H to $05FFH
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Flash Memory
60K bytes flash memory for program. Address is located from $1000h to $FFFFh.
The following addresses are reserved for special purpose :
$FFFAh (low byte) and $FFFBh (high byte) : INT0 interrupt vector.
$FFFCh (low byte) and $FFFDh (high byte) : program reset interrupt vector.
$FFFEh (low byte) and $FFFFh (high byte) : INT1 interrupt vector.
Weltrend Semiconductor, Inc.
Page 5
5 Page 
WT62P2 v1.04
USB Monitor Controller
I/O Port C
The structure of I/O Port C is same as Port B except the output low level has 10mA current sink
capability.
Port C Control Register
Name Addr R/W Initial Bit 7
PC_CTRL 0004h W 00h PC7OE
Bit 6
PC6OE
Bit 5
PC5OE
Bit4
PC4OE
Bit 3
PC3OE
Bit 2
PC2OE
Bit 1
PC1OE
Bit 0
PC0OE
Bit Name
Description
PCnOE
Port Cn Output Enable.
When it is set, PCn is output pin.
When it is cleared, PCn is input pin with internal pull high
Port C Data Register
Name Addr R/W Initial Bit 7 Bit 6 Bit 5
Bit4 Bit 3 Bit 2
Bit 1 Bit 0
PC_DATA 0005h R ffh PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
W 00h PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
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Bit Name
PCn (W)
PCn (R)
Description
This bit controls the output level when the corresponding PCnOE bit is set.
When PCn=1, PCn pin outputs high level.
When PCn=0, PCn pin outputs low level.
When PCnOE=1 (i.e. output port), this bit is same as PCn (W).
When PCnOE=0, this bit indicates the input level. “1” means high and “0” means low.
I/O Port D
I/O Port D is shared with some special functions. When the special function is disabled, it is an general
I/O port and is same as Port A2. If it is configured as an output, it can source/sink 6mA. If it is configured
as an input, it has an internal pull-up resistor.
Port D Control Register
Name Addr R/W Initial
PD_CTRL 0006h W 00h
Bit 7
--
Bit 6
--
Bit 5
Bit4 Bit 3 Bit 2
Bit 1 Bit 0
PD5OE PD4OE PD3OE PD2OE PD1OE PD0OE
Bit Name
PDnOE
Description
Port Dn Output Enable.
When it is set, PDn is output pin.
When it is cleared, PDn is input pin with internal pull high
Port D Data Register
Name Addr R/W Initial Bit 7 Bit 6 Bit 5
Bit4 Bit 3 Bit 2
Bit 1 Bit 0
PD_DATA 0007h R xfh
--
-- PD5 PD4 PD3 PD2 PD1 PD0
W x0h
--
-- PD5 PD4 PD3 PD2 PD1 PD0
Bit Name
PDn (W)
Description
This bit controls the output level when the corresponding PDnOE bit is set.
When PDn=1, PDn pin outputs high level.
When PDn=0, PDn pin outputs low level.
Weltrend Semiconductor, Inc.
Page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet WT62P2.PDF ] | |
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