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PDF AT24C11 Data sheet ( Hoja de datos )
| Número de pieza | AT24C11 | |
| Descripción | Two-wire Serial EEPROM | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Low Voltage and Standard Voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 5.5V)
• Internally Organized 128 x 8
• Two-wire Serial Interface
• Bidirectional Data Transfer Protocol
• 400 kHz (1.8V) and 1 MHz (2.5V, 2.7V, 5V) Compatibility
• 4-Byte Page Write Mode
• Self-Timed Write Cycle (5 ms max)
• High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
• Automotive Grade, Extended Temperature and Lead-Free/Halogen-Free
Devices Available
• 8-lead PDIP, 8-lead JEDEC SOIC, 5-lead SOT23 and 8-lead TSSOP Packages
• Die Sales: Wafer Form, Waffle Pack, and Bumped Wafers
• Access to One Additional Page Upon Request
Two-wire Serial
EEPROM
1K (128 x 8)
AT24C11
Description
The AT24C11 provides 1024 bits of serial electrically erasable and programmable
read only memory (EEPROM) organized as 128 words of 8 bits each. The device is
optimized for use in many industrial and commercial applications where low power
and low voltage operation are essential. The AT24C11 is available in space saving
8-lead PDIP, 8-lead JEDEC SOIC, 5-lead SOT23 and 8-lead TSSOP packages and is
accessed via a two-wire serial interface. In addition, the entire family is available in
2.7V (2.7V to 5.5V) and 1.8V (1.8V to 5.5V) versions.
Table 0-1.
Pin Name
NC
SDA
SCL
TEST
Pin Configuration
Function
No Connect
Serial Data
Serial Clock Input
Test Input (GND or VCC)
NC
NC
NC
GND
8-lead TSSOP
18
27
36
45
8-lead SOIC
VCC
TEST
SCL
SDA
NC
NC
NC
GND
1
2
3
4
8 VCC
7 TEST
6 SCL
5 SDA
8-lead PDIP
NC
NC
NC
GND
1
2
3
4
8 VCC
7 TEST
6 SCL
5 SDA
SCL
GND
SDA
5-lead SOT23
1 5 VCC
2
3 4 TEST
Note: Not recommended for new
design; please refer to
AT24C01B datasheet.
Rev. 3409G–SEEPR–8/07
1 page  
AT24C11
3. Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external
device. Data on the SDA pin may change only during SCL low time periods (see Figure 3-3 on
page 7). Data changes during SCL high periods will indicate a start or stop condition as defined
below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which
must precede any other command (see Figure 3-4 on page 7).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition which ter-
minates all communications. After a read sequence, the stop command will place the EEPROM
in a standby power mode (see Figure 3-4 on page 7).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. Any device on the system bus receiving data (when communicating
with the EEPROM) must pull the SDA bus low to acknowledge that it has successfully received
each word. This must happen during the ninth clock cycle after each word received and after all
other system devices have freed the SDA bus. The EEPROM will likewise acknowledge by pull-
ing SDA low after receiving each address or data word (see Figure 3-5 on page 7).
STANDBY MODE: The AT24C11 features a low power standby mode which is enabled: (a)
upon power-up and (b) after the receipt of the STOP bit and the completion of any internal
operations.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-wire part
can be reset by following these steps:
(a) clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then (c) create
a start condition as SDA is high.
3409G–SEEPR–8/07
5
5 Page 
6. Packaging Information
8P3 – PDIP
1
AT24C11
E
E1
N
Top View
c
eA
End View
D
e
D1 A2 A
b3
4 PLCS
b2
b
Side View
L
COMMON DIMENSIONS
(Unit of Measure = inches)
SYMBOL
A
A2
b
b2
b3
c
D
D1
E
E1
e
eA
L
MIN NOM MAX
0.210
0.115 0.130 0.195
0.014 0.018 0.022
0.045 0.060 0.070
0.030 0.039 0.045
0.008 0.010 0.014
0.355 0.365 0.400
0.005
0.300 0.310 0.325
0.240 0.250 0.280
0.100 BSC
0.300 BSC
0.115
NOTE
2
5
6
6
3
3
4
3
4
0.130
Notes:
1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
2325 Orchard Parkway
R San Jose, CA 95131
TITLE
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
DRAWING NO. REV.
8P3 B
3409G–SEEPR–8/07
11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet AT24C11.PDF ] | |
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