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PDF AT76C713 Data sheet ( Hoja de datos )
| Número de pieza | AT76C713 | |
| Descripción | USB BRIDGE CONTROLLER | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Advanced RISC Architecture, 130 Powerful Instructions, Most Single-Clock Cycle
Execution
• Clock Generator Provides CPU Rates up to 48 MHz
• Only One External Clock Crystal of 12 MHz Can Generate All the Required System
Clocks:
– Internal Clock for Standard UART Rates
– A 48 MHz and 96 MHz Clock for USB Data Recovery
– AVR Processor and System Clock
• Full-speed USB Interface (12 Mbits per Second) 2.0 Compliant
• JTAG (IEEE std. 1149.1 compliant) Interface
– Boundary-Scan Capabilities According to the JTAG Standard
– Extensive On-Chip Debug Support
• Two On-chip 16550 UARTs Supporting Baud Rates up to 921 Kbaud
– Both UARTs Incorporate Individual Transmit and Receive FIFOs of 16 Bytes
– UART0 Supports Modem Control Signals
• Programmable SPI Interface
• On-chip Bootstrap ROM Provides a Variety of Firmware Upgrade Modes
– Device Firmware Upgrade Through USB for the Internal Program SRAM
(No External Non-volatile SPI Memory Required)
– Device Firmware Upgrade Through USB for both the Internal Program SRAM and
the External SPI DataFlash® or EEPROM
– SPI Program Mode from the External DataFlash or EEPROM
• External Memory Interface Supporting up to 32 Kbytes of External RAM in Address
Multiplexed Mode, 2 Banks of 256 Bytes in Non-multiplexed Mode, FIFO, or with an
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Extra 20 GPIOs
• DMA Channels Allow Fast Data Transfers between Endpoint Buffers and Internal or
External SRAM (DMA Transfer Rate is 12 MHz for All Channels)
• 8K x 16 bits (up to 11K x 16 Bits), In-System SRAM for Program Code (Program
Memory)
• On-chip 8 Kbytes SRAM for Data and Variables (2, 4, or 6 Kbytes can be Remapped for
Program Storage in the Address Area Above the Program Memory
• Two 8-bit Timer/Counters
• One 16-bit Timer/Counter
• Four External Interrupts Through GPIOs
• Programmable Watchdog Timer
• Low Voltage Operation:
– 1.8V for the Core
– 1.8V or 3.3V for the Periphery
– 3.3V for the USB
• 100-pin TQFP Package
• Applications
– Programmable USB-to-Serial Bridge for RS-2332 Devices (Cell Phones, Printers,
PDAs, etc.)
– IrDA Control over USB
– USB Memory Sticks
– General High-speed Microcontroller Application
High-speed
(48 MHz) AVR®
Microcontroller
with USB
Interface
AT76C713
5665B–USB–04/05
ATMEL CONFIDENTIAL
1 page  
4. Pin Summary – Pin Assignment
AT76C713
Table 4-1.
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Pin Summary – Pin Assignment
Pin Name
Pin #
N/C 35
N/C 36
PGND
37
nRST
38
CVDD
39
PE7/nRD
40
PE6/nWR
41
PE5/nINT3
42
PE4/nINT2
43
PE3/nINT1
44
PE2/nINT0
45
PE1/SOUT1
46
PE0/SIN1
47
PVDD
48
PMODE0
49
PMODE1
50
CGND
51
PGND
52
LFT 53
PAGND
54
XIN 55
XOUT
56
PAVDD
57
N/C 58
PAVDD
59
PAGND
60
VEXT
61
POR_VSEL
62
PVDD
63
PC7/ALE
64
PC6/A14
65
PC5/A13
66
CGND
67
PC4/A12
68
5665B–USB–04/05
Pin Name
PC3/A11
PC2/A10
PC1/A9
PC0/A8
CVDD
PB7/SCK
PB6/MISO
PB5/MOSI
PB4/nSS
PB3/ICP
PB2/T2
PVDD
PGND
N/C
N/C
PVDD
PGND
N/C
PVDD_PORTD
PD7/RI
PD6/CD
PD5/DTR
PD4/DSR
PD3/CTS
PD2/RTS
PD1/SOUT0
PD0/SIN0
CVDD
PGND
CGND
SUSP
DP
DM
PVDD_USB
Pin #
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Pin Name
PA7
PA6
PA5
PA4
PA3
N/C
PVDD
PGND
N/C
PGND
PVDD
USB_ATTACH
TCK
TMS
TDI
TDO
CGND
nCS1
nCS0
nFWR
nFRD
CVDD
PA2
PA1
PA0
PB1/T1
PB0/T0
TEST_EN
TEST_CLK
PVDD
N/C
N/C
ATMEL CONFIDENTIAL
5
5 Page 
AT76C713
6.1.4
If the data fetched from the external serial memory is configuration parameters only, the boot-
strap code of the boot ROM will not switch to the program memory at the end of data fetching.
Instead, it will enable the USB controller. The USB will enumerate using the descriptors loaded
from the SPI memory. Upon enumeration completion, if a DFU application is enabled in the host,
then the bootstrap ROM will support program storing in the program memory through the USB.
When program storing is complete, the device will switch to the program memory.
Configuration Header
The Configuration Header is at least 256 bytes length and consumes the first page of the SPI
memory. For systems that use SPI slave programming or SPI EEPROM memory (for example,
AT25128A), the Configuration Header length is fixed to 256 bytes. For systems that use SPI
DataFlash, the page size is equal to the page size of the used DataFlash. For example, using
the AT45DB011B, the page size is 264 bytes and thus, the Configuration Header will consume
264 bytes.
The meaning of each byte is described in Table 6-3.
Table 6-3. Configuration Header
Byte
Description
0 $55
1 $AA
2 Size[7:0]
3 Size[15:8]
4 Control Byte
5 MEMMAP
Device descriptor
6 CIS[ ]
Configuration descriptor
Serial descriptor
Product descriptor
The first 2 bytes must be $55 and $AA in order to detect the rest of the information as valid. If
those bytes are invalid, then the bootstrap code rejects the operation immediately and starts the
USB DFU procedures.
Size[15:0] is the length of the image code counted in pages. During the slave programming
mode and the SPI EEPROM master programming mode, each page is 256 bytes long.
The control bitmap (or control byte) is described in Table 6-4.
5665B–USB–04/05
Table 6-4. Control Bitmap
Control Byte
Bit Field
Description
7 WSOF Wait USB SOF.
6 — Reserved to zero (‘0’).
5
PLCK
If set, then don’t use the PLL Lock signal (see also the PLCK bit of “Clock Control
Register (CLK_CNTR)” on page 51).
ATMEL CONFIDENTIAL
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AT76C713.PDF ] | |
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