PDF TSS463C Data sheet ( Hoja de datos )

Número de pieza	TSS463C
Descripción	VAN Data Link Controller
Fabricantes	ATMEL Corporation
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Features • Fully Compliant to VAN Specification ISO/11519-3 • Handles All Specified Module Types • Handles All Specified Message Types • Handles Retransmission of Frames on Contention and Errors • 3 Separate Line Inputs with Automatic Diagnosis and Selection • Normal or Pulsed (Optical and Radio Mode) Coding • VAN Transfer Rate: 1 Mbit/s Maximum • SPI/SCI Interface • SPI Transfer Rate: 4 Mbits/s Maximum SCI Transfer Rate: 125 Kbits/s Maximum • Idle and Sleep Modes • 128 Bytes of General Purpose RAM • 14 Identifier Registers with All Bits Individually Maskable • 6-source Maskable Interrupt Including an Interrupt-on-reset to Detect Glitches on the Reset Pin • Integrated Crystal or Resonator Oscillator with Internal Baud Rate Generator and Buffered Clock Output • Single +5V Power Supply • 0.5 μm CMOS Technology • SO16 Package VAN Data Link Controller with Serial Interface TSS463C Description The TSS463C is a circuit that allows the transfer of all the status information needed in a car or truck over a single low-cost wire pair, thereby minimizing electrical wire usage. It can be used to interconnect powerful functions and to control and interface car body electronics (lights, wipers, power window, etc.). www.DataShTeeht4Ue.coTm SS463C is fully compliant with the VAN ISO standard 11519-3. This standard supports a wide range of applications such as low-cost remote controlled switches, typically it is used for lamp control, up to complex, highly autonomous, distributed sys- tems that require fast and secure data transfers. The TSS463C is a microprocessor-interfaced line controller for mid-to-high complexity bus-masters and listeners like dashboard controllers, car stereo or mobile telephone CPUs. The microprocessor interface consists of a 256-byte RAM and a register area divided into 11 control registers, 14 channel register sets and 128 bytes of general-purpose RAM, used as a message storage area, and a 6-source maskable interrupt. The circuit operates in the RAM using DMA techniques, controlled by the channel and control registers. This allows virtually any microprocessor, including SPI/SCI interface, to be connected with ease to the TSS463C. Messages are encoded in enhanced Manchester code, and an optional pulsed code for use with an optical or radio link, at a maximum bit rate of 1 Mbit/s. The TSS463C analyzes the messages received or transmitted according to 6 different criteria includ- ing some higher level checks. In addition, the bus interface has three separate inputs with automatic source diagno- sis and selection, allowing for multibus listening or the automatic selection of the most reliable source at any time if several line receivers are connected to the same bus. 7601B–AUTO–02/06 1 1 page Microprocessor Interface Interface Modes Motorola SPI Mode TSS463C The processor controls the TSS463C by reading and writing the internal registers of the circuit. These registers appear to the processor as regular memory locations. The TSS463C must be connected with an SPI or SCI serial interface.The following sec- tion provides information switching from one mode to another. The first two bytes to be sent by the master (CPU) are called ’Initialization Sequence’: This sequence provides a proper asynchronous RESET in the TSS463C and it selects the Motorola SPI, Intel SPI or the SCI serial mode. This initialization sequence is shown on figure 4: two 0x00 will cause an internal RESET and assert the Motorola SPI mode, two ’0xFF’ will provide an internal RESET and assert the Intel SPI mode and ’9 bits to 0 followed by 0xFF or 0xFE’will generate an internal RESET and assert the 9-bits SCI mode. Figure 2. Mode Configuration Byte SCLK SPI 8 Pulses MOSI SS 0x00 or 0xFF 0x00 Motorola 0xFF Intel Internal RESET Internal RESET and SPI Mode (Intel or Motorola) SCLK MOSI SS SCI 9 Pulses 0 . 0000 . 0000 1 . 1111 . 1111 Internal RESET Internal RESET and SCI Mode The Motorola Serial Peripheral Interface (SPI) is fully compatible with the SPI Motorola protocol. The interface is implemented for slave-mode only (the TSS463C can not gen- erate SPI frames by itself). The SPI interface allows the interconnection of several CPUs and peripherals on the same printed circuit board. The SPI mode interface consists of 4 pins: separate wires are required for data and clock, so the clock is not included in the data stream as shown on Figure 3. One pin is needed for the serial clock (SCLK), two pins for data communication MOSI and MISO and one pin for Slave Select (SS) 7601B–AUTO–02/06 5 5 Page TSS463C Figure 8. SCI Speed Considerations 125 Kbits/s Max for SCLK SCLK MOSI Start Bit Address Stop Bit SS 4 Xtal Min (4 s at 1 MHz) 8 Xtal Min (8 s at 1 MHz) Control 15 Xtal Min (15 s at 1 MHz) Data 12 Xtal Min (12 s at 1 MHz) Interrupts Reset Asynchronous Reset Synchronous Reset If an event occurs in the TSS463C that needs the attention of the processor, this will be signalled on the active low, open drain interrupt request pin. The event that creates this request is controlled by the internal registers. Every time the microprocessor accesses any of the interrupt registers (addresses 0x08 to 0x0B), the INT pin will be released momentarily. This enables the TSS463C to work with processors that have either edge or level sensitive interrupt inputs. The reset is applied asynchronously or synchronously to the XTAL clock. It can be done either by the RESET pin (hardware asynchronous reset) or by software (software asynchronous reset). The RESET pin is a CMOS trigger input with a pull-up resistor (~ 70 kΩ). An external 1 μF capacitor to GND provides to RESET pin an efficient behavior. The asynchronous software reset is made by the ’Initialization Sequence’described in “Motorola SPI Mode” on page 5. Two ’0x00’bytes provide an asynchronous software reset and configure the TSS463C in the Motorola SPI mode while two ’0xFF’bytes provide a reset and configure the compo- nent in the Intel SPI mode and ’0x00 followed by 0xFF ’provide a reset and configure the component in the SCI mode. The SS pin must be asserted as shown on Figure 9. The SPI/SCI logic will monitor these two bytes and provide an internal reset pulse asserting the TSS463C in the right mode. A synchronous reset (regarding XTAL clock) is available on the TSS463C during current operation. It is made through the GRES command bit of the Command Register (address 0x03). The two kinds of reset are ordered and filtered. Then the internal reset, always asserted asynchronously, enables the internal oscillator. Then it waits for 12 clock periods and the oscillator stability. The different blocks of the TSS463C need to be turned on synchronously. So the release of the internal reset is synchronous and a loose of clock can let the TSS463C in permanent reset after applying Reset. It is important to note that even after a reset on the RESET pin, the user should wait for 12 clock periods before sending the ’Initialization Sequence’in order to select the SPI or SCI mode (because the default mode after a hardware reset is the Motorola SPI mode). 7601B–AUTO–02/06 11 11 Page

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