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IS23SC1604 데이터시트 PDF




ISSI에서 제조한 전자 부품 IS23SC1604은 전자 산업 및 응용 분야에서
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부품번호 IS23SC1604 기능
기능 16-KBIT SECURED SERIAL EEPROM
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IS23SC1604 데이터시트, 핀배열, 회로
IS23SC1604
16-KBIT SECURED SERIAL EEPROM
ISSI®
ADVANCE INFORMATION
APRIL 2003
FEATURES
• 16K serial EEPROM with security features
• Comply with ISO/IEC Standard 7816-3
Synchronous Protocol
• Store and validate security codes
• Four protected application zones
• Provide transport code security
• Single 5V power supply for read/write/erase
operations
• Low power operation:
— 15 µA (max.) standby current
— 3 mA (max.) read current at 300 KHz
— 4 mA (max.) write/erase current
• 2 ms read access time at 300 KHz;
5 ms write cycle time
• 300 KHz serial clock rate
www.DataSheet4U.com
• High ESD protection: > 4 KV
• High reliability:
— 1,000,000 erase/write cycles
— 10 years data retention
• Standard CMOS Process
• Wide operating temperature range
— 0°C to +70°C Commercial; –40°C to +85°C
Industrial
• Data access only after validation of security
code
• Permanent invalidation of device upon eight
consecutive failed attempts to enter the correct
security code
• Separate read/write/erase access protections
for each application zone
• Allow the memory chip to be personalized if the
internal security fuse is not blown. If the internal
security fuse is blown, maximum security protection
of the memory will always be enabled.
DESCRIPTION
IS23SC1604 is a low-cost, low-power, highly secured
16K bits (2K x 8) serial EEPROM. It is fabricated using
ISSI’s advanced CMOS technology.
The security features of IS23SC1604 provide high levels
of memory security protection for smart card applications.
The memory is partitioned into four application zones.
Each individual application zone is protected by multiple
security codes from unauthorized read/write/erase
access to the zone. In addition, an internal security fuse
is available for the card issuer to fully personalize the
device before releasing it to customer.
The device also features an internal high-voltage charge
pump for memory programming, 1,000,000 write/erase
cycles and ten years of data retention.
Pin Configuration: 8-pin Plastic DIP
Vcc
RST
CLK
FUS
C1
C2
C3
C4
C5 GND
C6 NC
C7 I/O
C8 PGM
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION Rev. 00E
04/10/03
1




IS23SC1604 pdf, 반도체, 판매, 대치품
IS23SC1604
ISSI®
IS23SC1604 OPERATIONS
Power-On Reset (POR)
When the supply voltage is first applied to the device,
the device initiates POR. All the internal flags are clear
(refer to Definition of IS23SC1604 Internal Flags), and
the internal address counter is reset to zero.
Reset
With CLK LOW, a HIGH-to-LOW transition at RST
resets the address counter to zero. After the falling edge
of RST, the device outputs the first bit of the memory on
I/O pin. The reset operation will have no effect on any
internal flags (see AC Test Load).
Addressing
Addressing is handled by an internal address counter
which is incremented on the falling edge of CLK. When
the counter continues to increment past 16383, the
counter will roll over back to zero. The counter can also
be cleared to zero by the reset operation.
Read
If read access to a memory bit is enabled, the state of
the bit can be read out of the device by incrementing
the address counter to the bit location. The device
outputs the state of the read bit on the I/O pin after the
falling edge of the last clock pulse that increments the
address counter to the read bit location. However, if the
read access to the memory bit is inhibited, the state of
the data bit will not be output and the I/O pin will be
placed in high-impedance state ‘1’ (see Reset Timing
Diagram).
Compare
Compare operation allows users to input the security/
erase key code for the security/erase key code valida-
tion for read/write/erase access to protected application
zones (refer to Security/Erase Key Code Validation
Operation).
The compare operation latches the user’s input Security/
Erase Key bit into the device at the rising edge of CLK
and the bit comparison is performed on the next falling
edge of CLK.The compare and read operations are
executed in the same manner. The device distinguishes
between the two operations by testing the address
counter for security/erase key code location and the
state of corresponding security/erase key code valid
comparison flag (see Read Timing Diagram).
Write
If write access to a memory bit is enabled, the content
of the bit can be written over with a ‘0’ value by perform-
ing the following sequence: select PGM (logic HIGH
state), input ‘0’ on the I/O pin, change CLK from LOW-
to-HIGH, deselect PGM (logic LOW state), wait for 5 ms
programming delay, and then bring CLK down from
HIGH-to-LOW to complete the write operation. The new
state of the bit will be output at the end of the write
operation after the falling edge of CLK for data verifica-
tion (see Compare Timing Diagram).
Erase
If erase access to a memory bit is enabled, the content
of the bit can be written over with a ‘1’ value with the
erase operation. Although erase is performed on single
bits, the erase operation writes FFH to the whole byte
which contains the erased bits because the memory is
organized into 8-bit bytes. The erase operation can be
executed by performing the following sequence: select
PGM (logic HIGH state), input ‘1’ on the I/O pin, change
CLK from LOW-to-HIGH, deselect PGM (logic LOW
state), wait for 5 msec programming delay, and then
bring CLK down from HIGH-to-LOW to complete the
erase operation. The new state of the bit will be output
at the end of the erase operation after the falling edge of
CLK for data verification (see Compare Timing Dia-
gram).
4 Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCEINFORMATION Rev. 00E
04/10/03

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IS23SC1604 전자부품, 판매, 대치품
IS23SC1604
AC Test Conditions
Parameter
Input Pulse Levels
Input Rise and Fall Time
Input and Output Timing and Reference Level
Output Load
AC Test Load
GND
Value
GND to 3.0V
5 ns
0.8V and 2.0V
100 pF
Chip
4.7K
Test Point
100 pF
I/O
ISSI®
AC Electrical Characteristics (TA = 0 to 70°C, Vcc = 5.0V + 10%; GND = 0V)
Symbol
fCLK
tCLK
tRH
tDVR
tCH
tCL
tDV
tOH
tSC
tHC
tCHP
tDS
tDH
tSPR
tHPR
Parameter
Clock Frequency
Clock Cycle Time
RST Hold Time
Data Valid Reset to Address 0
CLK Pulse Width (High)
CLK Pulse Width (Low)
Data Access
Data Hold
Data in Setup (CMP Instruction)
Data in Hold (CMP Instruction)
CLK Pulse Width (High in Erase/Write)
Data in Setup
Data in Hold
PGM Setup
PGM Hold
Min. Typ. Max.
— — 300
3.3 — —
0.1 — —
— — 2.0
0.2 — —
0.2 — —
— — 2.0
0 ——
0 ——
0.2 — —
5.0 — —
0.2 — —
0 ——
2.2 — —
0.2 — —
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION Rev. 00E
04/10/03
Unit
KHz
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
7

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IS23SC1604

16-KBIT SECURED SERIAL EEPROM

ISSI
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