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PDF LP3927ILQ-AJ Data sheet ( Hoja de datos )
| Número de pieza | LP3927ILQ-AJ | |
| Descripción | Cellular/PCS System Power Management IC | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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August 2002
LP3927
Cellular/PCS System Power Management IC
General Description
The LP3927 system power management IC is designed for
cellular/PCS handsets as well as other portable systems that
require intelligent power management. Each device contains
five low-dropout linear regulators (LDO’s), a reset timer, a
power-up control logic, a general-purpose open drain output
that can be used to light LEDs, and a CMOS rail-to-rail
input/output operational amplifier.
Each linear regulator features an extremely low dropout
voltage of 100 mV (typ) at maximum output current. LDO1
and LDO2 are powered on and off by either the KYBD or the
VEXT pin. LDO3, LDO4 and LDO5 each have its indepen-
dent enable pin. LDO1 and LDO4 are rated at 150 mA each,
LDO2 and LDO5 are rated at 200 mA each and LDO3 is
rated at 100 mA. All LDO’s are optimized for low noise and
high isolation.
The open drain output current sink can be programmed up to
150 mA by using an external low cost resistor.
A single supply, low voltage operational amplifier has rail to
rail input and output with 600 kHz of gain-bandwidth product.
Key Specifications
n 3.0V to 5.5V Input Voltage Range
n Two 200 mA, Two 150 mA and One 100 mA LDO’s
n 100 mV typ Dropout Voltage @ IMAX
n 150 mA General-Purpose Open-drain programmable
current sink for back light LED
n Low Voltage Rail to Rail Input/Output Operational
Amplifier
n 28 pin LLP package
Applications
n Cellular/PCS handsets
n PDA’s, Palmtops, and portable terminals
n Single–Cell Li+ Systems
n 2- or 3- Cell NiMH, NiCd or Alkaline System
Typical Application Circuit
VDD1, VDD2 and VDD3 must be tied together externally. Collectively called VDD.
© 2002 National Semiconductor Corporation DS200379
20037901
www.national.com
1 page  
Absolute Maximum Ratings (Notes 1,
2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
All pins except LED_PGM,
BYP, op amp’s inputs & output
OP_AMP_OUT, IN-, IN+
GND to GND SLUG
Junction Temperature
Storage Information
Soldering Temperature
Pad Temperature
Maximum Power Dissipation (Note 3)
ESD (Note 4):
KYBD
−0.3V to 6.0V
-0.3V to 5.5V
±0.3V
150˚C
−65˚C to 150˚C
235˚C
2.6W
4 kV
All other pins
2 kV
Operating Ratings (Notes 1, 2)
VDD1, VDD2, VDD3, KYBD, OP_AMP_VDD 3.0V to 5.5V
EN3, EN4, EN5
−0.3V to (VDD + 0.3V)
COUT:
Capacitance
1.0 µF to 20.0 µF
ESR
0.005Ω to 0.5Ω
Junction Temperature
−40˚C to 125˚C
Operating Temperature
−40˚C to 85˚C
Thermal Resistance (Note 5)
θJA (LLP28)
Maximum Power Dissipation (Note 6)
30.8˚C/W
1.78W
Electrical Characteristics, LDO’s
Unless otherwise noted, VDD = VOUT(target) + 0.7V, CIN (VDD1, VDD2, VDD3) = 4.7 µF, COUT (VO1 to VO5) = 2.2 µF, Cbyp =
0.1 µF. Typical values and limits appearing in normal type apply for TJ = 25˚C. Limits appearing in boldface type apply over
the entire junction temperature range for operation, −40˚C to +85˚C. (Notes 7, 8)
Symbol
Parameter
Conditions
Typical
Limit
Min Max
Units
VDD
∆VOUT
Input Voltage Range
Output Voltage Tolerance
Load Regulation
Line Regulation
Total Accuracy Error
VDD1, VDD2, VDD3,KYBD
IOUT = IMAX/2,
VDD = 3.7V
IOUT = 100 µA to IMAX,
VDD = 3.7V
VDD = VOUT(target) +0.7V to 5.5V
IOUT = IMAX/2
3.7 3 5.5
−2 +2
−2 +2
−40 +40
−3.5 +3.5
V
%
%
mV
%
VIN - VOUT Dropout Voltage
IOUT = IMAX (Note 9)
100 170 mV
200
eN
PSRR
Output Noise Voltage
Power Supply Ripple
Rejection Ratio
IOUT = 100 µA,
10 Hz ≤ f ≤ 100 kHz
CIN = 2.2µF, IOUT = IMAX,
f = 100 Hz
f = 1 kHz
f = 10 kHz
f = 100 kHz
27
45
45
30
10
µVrms
dB
Cross Talk
(Note 10)
30 dB
IQ
IGND
Quiescent Current
Ground Current
IOUT = 0, PS_HOLD = KYBD = 0
VEXT = VDD
IOUT1 = IOUT2 = 1 mA,
LDO3, LDO4, LDO5 OFF
100
5 µA
8
200 µA
ISC
COUT
RSHUNT
Short Circuit Current Limit
Output Capacitor
VO2 - VO5 Output Shunt
Resistor
IOUT1, IOUT2, IOUT3, IOUT4, IOUT5 = IMAX
VOUT = 0V
Capacitance
ESR
400
400
70
950
% of IMAX
1 20
µF
5 500
mΩ
200 Ω
5 www.national.com
5 Page 
Keyboard Held at Start-Up/Shut-Down
Note: Diagram indicates Open Drain IRQ tied to VDD.
*** = Internal signal
1. Keyboard de-bounce delay, 32msec typ.
2. Delay between LDO1 reaching 95% of its output voltage and LDO2 enable.
3. Both LDO1 and LDO2 outputs reach 95% of the respective output voltage, start RST timer.
4. Reset delay.
5. IRQ is active low.
6. Keyboard press must be greater than 32 msec.
7. PS_HOLD timer begins upon RST going high.
8. Maximum of 500 msec period from RST going high to PS_HOLD going high.
9. Response time from PS_HOLD going low to RST going low.
10. Delay between RST high-low transition to LDO2 disable.
11. Delay between LDO2 disable and LDO1 disable.
20037926
11 www.national.com
11 Page | ||
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| PDF Descargar | [ Datasheet LP3927ILQ-AJ.PDF ] | |
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