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PDF NL17SV32XV5T2 Data sheet ( Hoja de datos )
| Número de pieza | NL17SV32XV5T2 | |
| Descripción | Single Gate 2-Input OR Gate | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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NL17SV32XV5T2
Single Gate 2−Input OR Gate
The NL17SV32 is an ultra−high performance 2 input OR gate
manufactured in 0.35 m CMOS technology with excellent performance
down to 0.9 volts. This device is ideal for extremely high−speed and
high−drive applications. Additionally, limitations of board space are
no longer a constraint. The very small SOT−553 makes this device fit
most tight designs and spaces.
Features
• Extremely High Speed: tPD = 1.0 ns (Typ) at VCC = 3.3 V
• Designed for 0.9 to 3.3 V Operation
• Overvoltage Tolerance (OVT)* Input Pins Permit Logic Translation
• Balanced "24 mA Output Drive @ 3.3 Volts
• Near Zero Static Supply Current
• Ultra−Tiny SOT−553 5 Pin Package Only 1.6 x 1.6 x 0.6 mm
• All Devices in Package SOT−553 are Inherently Pb−Free**
Typical Applications
• Cellular
• Digital Camera
• PDA
• Digital Video
www.DataSheet4U.com
Important Information
• High ESD Ratings for Handling:
Human Body Model: 2000 V
Machine Model: 200 V
• Latchup Max Rating: 500 mA
Industry Standard
• Compatible with Fairchild’s NC7SV32 and TI’s SN74AUC1G32
FUNCTION TABLE
Input A
Input B
Output Y
LLL
L HH
HLH
HHH
*Overvoltage Tolerance (OVT) enables input pins to function outside (higher) of
their operating voltages, with no damage to the devices or to signal integrity.
**For additional information on our Pb−Free strategy and soldering details,
please download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
http://onsemi.com
5
1
SOT−553
CASE 463B
MARKING
DIAGRAM
UM D
UM = Specific Device Code
D = Date Code
PIN DIAGRAM
A1
5 VCC
B2
GND 3
4Y
PIN ASSIGNMENT
1
Input
A
2
Input
B
3
GND
−
4
Output
Y
5
VCC
−
ORDERING INFORMATION
Device
Package
Shipping†
NL17SV32XV5T2 SOT−553 4000 Tape & Reel
(Pb−Free)
(178 mm)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2005
January, 2005 − Rev. 1
1
Publication Order Number:
NL17SV32XV5T2/D
1 page  
NL17SV32XV5T2
PACKAGE DIMENSIONS
SOT−553
5−LEAD PACKAGE
CASE 463B−01
ISSUE A
A
−X− C
54
12 3
B
−Y−
D 5 PL
G 0.08 (0.003) M X Y
K
S
J
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETERS
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A 1.50 1.70 0.059 0.067
B 1.10 1.30 0.043 0.051
C 0.50 0.60 0.020 0.024
D 0.17 0.27 0.007 0.011
G 0.50 BSC
0.020 BSC
J 0.08 0.18 0.003 0.007
K 0.10 0.30 0.004 0.012
S 1.50 1.70 0.059 0.067
SOLDERING FOOTPRINT*
0.3
0.0118
1.35
0.0531
1.0
0.0394
0.45
0.0177
0.5 0.5
0.0197 0.0197
ǒ ǓSCALE 20:1
mm
inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet NL17SV32XV5T2.PDF ] | |
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