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PDF FDD8424H Data sheet ( Hoja de datos )
| Número de pieza | FDD8424H | |
| Descripción | Dual N & P-Channel PowerTrench MOSFET | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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FDD8424H
Dual N & P-Channel PowerTrench® MOSFET
N-Channel: 40V, 20A, 24mΩ P-Channel: -40V, -20A, 54mΩ
March 2007
tm
Features
Q1: N-Channel
Max rDS(on) = 24mΩ at VGS = 10V, ID = 9.0A
Max rDS(on) = 30mΩ at VGS = 4.5V, ID = 7.0A
Q2: P-Channel
Max rDS(on) = 54mΩ at VGS = -10V, ID = -6.5A
Max rDS(on) = 70mΩ at VGS = -4.5V, ID = -5.6A
Fast switching speed
RoHS Compliant
General Description
These dual N and P-Channel enhancement mode Power
MOSFETs are produced using Fairchild Semiconductor’s
advanced PowerTrench- process that has been especially
tailored to minimize on-state resistance and yet maintain
superior switching performance.
Application
Inverter
H-Bridge
D1 D2
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D1/D2
G2
S2
G1
S1
G1
S1
Dual DPAK 4L
N-Channel
MOSFET Maximum Ratings TC = 25°C unless otherwise noted
G2
S2
P-Channel
Symbol
VDS
VGS
ID
PD
EAS
TJ, TSTG
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current - Continuous (Package Limited)
- Continuous (Silicon Limited)
- Continuous
- Pulsed
Power Dissipation for Single Operation
Single Pulse Avalanche Energy
Operating and Storage Junction Temperature Range
TC = 25°C
TA = 25°C
TC = 25°C (Note 1)
TA = 25°C (Note 1a)
TA = 25°C (Note 1b)
(Note 3)
Q1 Q2
40 -40
±20 ±20
20 -20
26 -20
9.0 -6.5
55 -40
30 35
3.1
1.3
29 33
-55 to +150
Thermal Characteristics
Units
V
V
A
W
mJ
°C
RθJC
RθJC
Thermal Resistance, Junction to Case, Single Operation for Q1
Thermal Resistance, Junction to Case, Single Operation for Q2
Package Marking and Ordering Information
(Note 1)
(Note 1)
4.1
3.5
°C/W
Device Marking
FDD8424H
Device
FDD8424H
Package
TO-252-4L
Reel Size
13”
Tape Width
12mm
Quantity
2500 units
©2007 Fairchild Semiconductor Corporation
FDD8424H Rev.C
1
www.fairchildsemi.com
1 page  
Typical Characteristics (Q1 N-Channel)TJ = 25°C unless otherwise noted
10
ID = 9A
8
2000
1000
Ciss
6
VDD = 15V
VDD = 20V
4
VDD = 25V
2
0
0 4 8 12 16
Qg, GATE CHARGE(nC)
Figure 7. Gate Charge Characteristics
30
TJ = 25oC
10
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TJ = 125oC
1
0.001
0.01 0.1 1 10
tAV, TIME IN AVALANCHE(ms)
Figure9. Unclamped Inductive
Switching Capability
100
100
10us
10 100us
THIS AREA IS
LIMITED BY rDS(on)
1 SINGLE PULSE
TJ = MAX RATED
RθJC = 4.1oC/W
0.1
1
TC = 25oC
10
1ms
10ms
DC
80
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 11. Forward Bias Safe
Operating Area
Coss
100
f = 1MHz
VGS = 0V
Crss
30
0.1
1 10
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure8. Capacitance vs Drain
to Source Voltage
40
30
25 Limited by Package
20
VGS = 10V
15
10
VGS = 4.5V
5
RθJC = 4.1oC/W
0
25 50 75 100 125
TC, CASE TEMPERATURE (oC)
Figure10. Maximum Continuous Drain
Current vs CaseTemperature
150
10000
1000
100
VGS = 10V
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
I = I25
1----5---0-----–----T----C---
125
TC = 25oC
10
10-5
SINGLE PULSE
RθJC = 4.1oC/W
10-4
10-3
10-2
10-1
t, PULSE WIDTH (s)
100
Figure 12. Single Pulse Maximum
Power Dissipation
101
©2007 Fairchild Semiconductor Corporation
FDD8424H Rev.C
5
www.fairchildsemi.com
5 Page 
www.DataSheet4U.com
©2007 Fairchild Semiconductor Corporation
FDD8424H Rev.C
11
www.fairchildsemi.com
11 Page | ||
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| PDF Descargar | [ Datasheet FDD8424H.PDF ] | |
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