PDF CS42416 Data sheet ( Hoja de datos )

Número de pieza	CS42416
Descripción	Surround-sound Codecs
Fabricantes	Cirrus Logic
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No Preview Available ! CS42416 110 dB, 192 kHz 6-Ch Codec with PLL Features z Six 24-bit D/A, two 24-bit A/D converters z 110 dB DAC / 114 dB ADC dynamic range z -100 dB THD+N z System sampling rates up to 192 kHz z Integrated low-jitter PLL for increased system jitter tolerance z PLL clock or OMCK system clock selection z 7 configurable general purpose outputs z ADC high pass filter for DC offset calibration z Expandable ADC channels and one-line mode support z Digital output volume control with soft ramp z Digital +/-15 dB input gain adjust for ADC z Differential analog architecture z Supports logic levels between 5 V and 1.8 V General Description The CS42416 CODEC provides two analog-to-digital and six digital-to-analog Delta-Sigma converters, as well as an inte- grated PLL, in a 64-pin LQFP package. The CS42416 integrated PLL provides a low-jitter system clock. The internal stereo ADC is capable of independent chan- nel gain control for single-ended or differential analog inputs. All six channels of DAC provide digital volume control and dif- ferential analog outputs. The general purpose outputs may be driven high or low, or mapped to a variety of DAC mute controls or ADC overflow indicators. The CS42416 is ideal for audio systems requiring wide dynam- ic range, negligible distortion and low noise, such as A/V receivers, DVD receivers, digital speaker and automotive audio systems. ORDERING INFORMATION CS42416-CQ* -10° to 70° C CS42416-DQ* -40° to 85° C CDB42428 Evaluation Board 64-pin LQFP 64-pin LQFP www.DataSheet4U.com *Also available in Lead-Free package GPO1 GPO2 GPO3 GPO4 GPO5 GPO6 GPO7 MUTEC AINL+ AINL- AINR+ AINR- AOUTA1+ AOUTA1- AOUTB1+ AOUTB1- AOUTA2+ AOUTA2- AOUTB2+ AOUTB2- AOUTA3+ AOUTA3- AOUTB3+ AOUTB3- VA AGND GPO ADC#1 ADC#2 REFGND VQ FILT+ OMCK RMCK LPFLT VLC DGND VD Mute Internal Voltage Reference Mult/Div PLL Control Port INT RST AD0/CS AD1/CDIN SDA/CDOUT SCL/CCLK Digital Filter Digital Filter DAC#1 DAC#2 DAC#3 DAC#4 DAC#5 DAC#6 Gain & Clip Gain & Clip ADC Serial Audio Port ADCIN1 ADCIN2 ADC_SDOUT ADC_LRCK ADC_SCLK VLS DAC_LRCK DAC_SCLK DAC_SDIN1 DAC_SDIN2 DAC_SDIN3 Advance Product Information Cirrus Logic, Inc. www.cirrus.com This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright  Cirrus Logic, Inc. 2003 (All Rights Reserved) MAY ‘03 DS602A1 1 1 page CS42416 Figure 52. Quad Speed (slow) Stopband Rejection...................................................................... 60 Figure 53. Quad Speed (slow) Transition Band ............................................................................ 60 Figure 54. Quad Speed (slow) Transition Band (detail) ................................................................ 60 Figure 55. Quad Speed (slow) Passband Ripple .......................................................................... 60 Figure 56. Serial Audio Port Master Mode Timing ........................................................................ 61 Figure 57. Serial Audio Port Slave Mode Timing .......................................................................... 61 Figure 58. Control Port Timing - I2C Format................................................................................. 62 Figure 59. Control Port Timing - SPI Format................................................................................. 63 LIST OF TABLES www.DataSheet4U.com Table 1. PLL External Component Values .................................................................................... 15 Table 2. Common OMCK Clock Frequencies .............................................................................. 15 Table 3. Common PLL Output Clock Frequencies....................................................................... 16 Table 4. Slave Mode Clock Ratios ............................................................................................... 16 Table 5. Serial Audio Port Channel Allocations ............................................................................ 17 Table 6. DAC De-Emphasis .......................................................................................................... 34 Table 7. Digital Interface Formats ................................................................................................. 35 Table 8. ADC One_Line Mode ...................................................................................................... 35 Table 9. DAC One_Line Mode ...................................................................................................... 35 Table 10. RMCK Divider Settings ................................................................................................. 37 Table 11. OMCK Frequency Settings ........................................................................................... 38 Table 12. Master Clock Source Select.......................................................................................... 38 Table 13. PLL Clock Frequency Detection.................................................................................... 39 Table 14. Example Digital Volume Settings .................................................................................. 42 Table 15. ATAPI Decode .............................................................................................................. 44 Table 16. Example ADC Input Gain Settings ................................................................................ 45 5 5 Page CS42416 3.2.2 External Input Filter The analog modulator samples the input at 6.144 MHz (internal MCLK=12.288 MHz). The digital filter will reject signals within the stopband of the filter. However, there is no rejection for input signals which are (n × 6.144 MHz) the digital passband frequency, where n=0,1,2,... Refer to the CDB42418 for a rec- ommended analog input buffer that will attenuate any noise energy at 6.144 MHz, in addition to providing the optimum source impedance for the modulators. The use of capacitors which have a large voltage coef- ficient (such as general purpose ceramics) must be avoided since these can degrade signal linearity. 3.2.3 High Pass Filter and DC Offset Calibration The high pass filter continuously subtracts a measure of the DC offset from the output of the decimation filter. The high pass filter can be independently enabled and disabled. If the HPF_Freeze bit is set during normal operation, the current value of the DC offset for the corresponding channel is frozen and this DC offset will continue to be subtracted from the conversion result. This feature makes it possible to perform a system DC offset calibration by: 1) Running the CS42416 with the high pass filter enabled until the filter settles. See the Digital Filter Characteristics for filter settling time. 2) Disabling the high pass filter and freezing the stored DC offset. The high pass filters are controlled using the HPF_FREEZE bit in the register “Misc Control (address 05h)” on page 36. 3.3 Analog Outputswww.DataSheet4U.com 3.3.1 Line Level Outputs and Filtering The CS42416 contains on-chip buffer amplifiers capable of producing line level differential outputs. These amplifiers are biased to a quiescent DC level of approximately VQ. The delta-sigma conversion process produces high frequency noise beyond the audio passband, most of which is removed by the on-chip analog filters. The remaining out-of-band noise can be attenuated using an off-chip low pass filter. The recommended output filter configuration is shown in the CDB42418. This filter configuration accounts for the normally differing AC loads on the AOUT+ and AOUT- differential output pins. It also shows an AC coupling configuration which minimizes the number of required AC cou- pling capacitors. 11 11 Page

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