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부품번호 | CS42438 기능 |
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기능 | Surround-sound Codecs | ||
제조업체 | Cirrus Logic | ||
로고 | |||
전체 30 페이지수
CS42438
108 dB, 192 kHz 6-In, 8-Out TDM CODEC
FEATURES
Six 24-bit A/D, Eight 24-bit D/A Converters
ADC Dynamic Range
– 105 dB Differential
– 102 dB Single-Ended
DAC Dynamic Range
– 108 dB Differential
– 105 dB Single-Ended
ADC/DAC THD+N
– -98 dB Differential
– -95 dB Single-Ended
Compatible with Industry-Standard Time
Division Multiplexed (TDM) Serial Interface
DAC Sampling Rates up to 192 kHz
ADC Sampling Rates up to 96 kHz
Programmable ADC High-Pass Filter for DC
Offset Calibration
www.DataSheet4U.com Logarithmic Digital Volume Control
Hardware Mode or Software I²C® & SPI™
Supports Logic Levels Between 5 V and 1.8 V
GENERAL DESCRIPTION
The CS42438 CODEC provides six multi-bit analog-to-
digital and eight multi-bit digital-to-analog delta-sigma
converters. The CODEC is capable of operation with ei-
ther differential or single-ended inputs and outputs, in a
52-pin MQFP package.
Six fully differential, or single-ended, inputs are avail-
able on stereo ADC1, ADC2, and ADC3. When
operating in Single-ended Mode, an internal MUX be-
fore ADC3 allows selection from up to four single-ended
inputs. Digital volume control is provided for each ADC
channel, with selectable overflow detection.
All eight DAC channels provide digital volume control
and can operate with differential or single-ended
outputs.
An auxiliary serial input is available for an additional two
channels of PCM data.
The CS42438 is available in a 52-pin MQFP package in
Commercial (-10° to +70°) and Automotive (-40° to
+105°) grades. The CDB42438 Customer Demonstra-
tion board is also available for device evaluation and
implementation suggestions. Please refer to “Ordering
Information” on page 61 for complete ordering
information.
The CS42438 is ideal for audio systems requiring wide
dynamic range, negligible distortion and low noise, such
as A/V receivers, DVD receivers, and automotive audio
systems.
Control Port & Serial
Audio Port Supply =
1.8 V to 5 V
Digital Supply =
3.3 V
Hardware Mode or
I2C/SPI Software Mode
Control Data
Reset
Register
Configuration
Analog Supply =
3.3 V to 5 V
Internal Voltage
Reference
TDM Serial Audio
Input
Auxilliary Serial
Audio Input
Input Master
Clock
TDM Serial Audio
Output
http://www.cirrus.com
Volume
Controls
Digital
Filters
∆Σ
Modulators
Multibit
DAC1-4 and
Analog Filters
8
8
Differential or
Single-Ended
Outputs
High Pass
Filter
High Pass
Filter
Digital
Filters
Digital
Filters
Multibit
Oversampling
ADC1&2
Multibit
Oversampling
ADC3
4
4 Differential or
Single-Ended
Analog Inputs
2
2
*Optional MUX allows selection from up to 4 single-ended inputs.
Copyright © Cirrus Logic, Inc. 2006
(All Rights Reserved)
AUGUST '06
DS646F1
CS42438
8.2 DAC Output Filter ........................................................................................................................... 53
9. ADC FILTER PLOTS............................................................................................................................. 54
10. DAC FILTER PLOTS........................................................................................................................... 56
11. PARAMETER DEFINITIONS............................................................................................................... 58
12. REFERENCES..................................................................................................................................... 59
13. PACKAGE INFORMATION................................................................................................................. 60
13.1 Thermal Characteristics ............................................................................................................. 60
14. ORDERING INFORMATION ............................................................................................................... 61
15. REVISION HISTORY ........................................................................................................................... 61
LIST OF FIGURES
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Figure 1.Typical Connection Diagram (Software Mode) ........................................................................... 11
Figure 2.Typical Connection Diagram (Hardware Mode) .......................................................................... 12
Figure 3.Output Test Circuit for Maximum Load ....................................................................................... 19
Figure 4.Maximum Loading ....................................................................................................................... 19
Figure 5.TDM Serial Audio Interface Timing ............................................................................................. 21
Figure 6.Serial Audio Interface Slave Mode Timing .................................................................................. 22
Figure 7.Control Port Timing - I²C Format ................................................................................................. 23
Figure 8.Control Port Timing - SPI Format ................................................................................................ 24
Figure 9.Full-Scale Input ........................................................................................................................... 28
Figure 10.ADC3 Input Topology ................................................................................................................ 28
Figure 11.Audio Output Initialization Flow Chart ....................................................................................... 31
Figure 12.Full-Scale Output ...................................................................................................................... 32
Figure 13.De-Emphasis Curve .................................................................................................................. 33
Figure 14.TDM Serial Audio Format ......................................................................................................... 34
Figure 15.AUX I²S Format ......................................................................................................................... 34
Figure 16.AUX Left-Justified Format ......................................................................................................... 35
Figure 17.Control Port Timing in SPI Mode .............................................................................................. 36
Figure 18.Control Port Timing, I²C Write ................................................................................................... 36
Figure 19.Control Port Timing, I²C Read ................................................................................................... 37
Figure 20.Single to Differential Active Input Filter ..................................................................................... 50
Figure 21.Single-Ended Active Input Filter ................................................................................................ 50
Figure 22.Passive Input Filter ................................................................................................................... 51
Figure 23.Passive Input Filter w/Attenuation ............................................................................................. 52
Figure 24.Active Analog Output Filter ....................................................................................................... 53
Figure 25.Passive Analog Output Filter .................................................................................................... 53
Figure 26.SSM Stopband Rejection .......................................................................................................... 54
Figure 27.SSM Transition Band ................................................................................................................ 54
Figure 28.SSM Transition Band (Detail) ................................................................................................... 54
Figure 29.SSM Passband Ripple .............................................................................................................. 54
Figure 30.DSM Stopband Rejection .......................................................................................................... 54
Figure 31.DSM Transition Band ................................................................................................................ 54
Figure 32.DSM Transition Band (Detail) ................................................................................................... 55
Figure 33.DSM Passband Ripple .............................................................................................................. 55
Figure 34.SSM Stopband Rejection .......................................................................................................... 56
Figure 35.SSM Transition Band ................................................................................................................ 56
Figure 36.SSM Transition Band (detail) .................................................................................................... 56
Figure 37.SSM Passband Ripple .............................................................................................................. 56
Figure 38.DSM Stopband Rejection .......................................................................................................... 56
Figure 39.DSM Transition Band ................................................................................................................ 56
Figure 40.DSM Transition Band (detail) .................................................................................................... 57
Figure 41.DSM Passband Ripple .............................................................................................................. 57
Figure 42.QSM Stopband Rejection ......................................................................................................... 57
4 DS646F1
4페이지 AUX_SCLK
AUX_SDIN
AOUT1 +,-
AOUT2 +,-
AOUT3 +,-
AOUT4 +,-
AOUT5 +,-
AOUT6 +,-
AOUT7 +,-
AOUT8 +,-
AGND
VQ
VA
AIN1 +,-
AIN2 +,-
AIN3 +,-
AIN4 +,-
AIN5 +,-
AIN6 +,-
AIN5 A,B
AIN6 A,B
FILT+
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CS42438
16 Auxiliary Serial Clock (Output) - Serial clock for the Auxiliary serial audio interface.
17
Auxiliary Serial Input (Input) - The 42438 provides an additional serial input for two’s comple-
ment serial audio data.
20,19
21,22
24,23
25,26
28,27
29,30
Differential Analog Output (Output) - The full-scale differential analog output level is specified in
the Analog Characteristics specification table. Each positive leg of the differential outputs may
also be used single-ended.
31,32
33,34
35,48 Analog Ground (Input) - Ground reference for the analog section.
36 Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage.
37,46 Analog Power (Input) - Positive power supply for the analog section.
39,38
41,40
43,42
45,44
50,49
52,51
Differential Analog Input (Input) - Signals are presented differentially to the delta-sigma modula-
tors. The full-scale input level is specified in the Analog Characteristics specification table. Single-
ended inputs may be applied to the positive terminals when the ADCx SINGLE bit is enabled.
Once in Single-Ended Mode, the negative terminal of AIN1-AIN4 must be externally driven to
common mode. See below for a description of AIN5-AIN6 in Single-Ended Mode.
Single-Ended Analog Input (Input) - In Single-Ended Mode, an internal analog mux allows
50,49 selection between two channels for both analog inputs AIN5 and AIN6 (see Sections 7.6.6-7.6.8
52,51 for details). The unused leg of each input is internally connected to common mode. The full-scale
input level is specified in the Analog Characteristics specification table.
47
Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling cir-
cuits.
DS646F1
7
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