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CS42448 데이터시트 PDF




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부품번호 CS42448 기능
기능 Surround-sound Codecs
제조업체 Cirrus Logic
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CS42448 데이터시트, 핀배열, 회로
CS42448
108 dB, 192 kHz 6-In, 8-Out CODEC
FEATURES
GENERAL DESCRIPTION
 Six 24-bit A/D, Eight 24-bit D/A Converters
 ADC Dynamic Range
– 105 dB Differential
– 102 dB Single-Ended
 DAC Dynamic Range
– 108 dB Differential
– 105 dB Single-Ended
 ADC/DAC THD+N
– -98 dB Differential
– -95 dB Single-Ended
 Compatible with Industry-Standard Time
Division Multiplexed (TDM) Serial Interface
 System Sampling Rates up to 192 kHz
 Programmable ADC High-Pass Filter for DC
Offset Calibration
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
Logarithmic Digital Volume Control
 I²C® & SPIHost Control Port
 Supports Logic Levels Between 5 V and 1.8 V
 Popguard® Technology
The CS42448 CODEC provides six multi-bit analog-to-
digital and eight multi-bit digital-to-analog delta-sigma
converters. The CODEC is capable of operation with ei-
ther differential or single-ended inputs and outputs, in a
64-pin LQFP package.
Six fully differential, or single-ended, inputs are avail-
able on stereo ADC1, ADC2, and ADC3. When
operating in Single-ended Mode, an internal MUX be-
fore ADC3 allows selection from up to four single-ended
inputs. Digital volume control is provided for each ADC
channel, with selectable overflow detection.
All eight DAC channels provide digital volume control
and can operate with differential or single-ended
outputs.
An auxiliary serial input is available for an additional two
channels of PCM data.
The CS42448 is available in a 64-pin LQFP package in
Commercial (-10° to +70°) and Automotive (-40° to
+105°) grades. The CDB42448 Customer Demonstra-
tion board is also available for device evaluation and
implementation suggestions. Please refer to “Ordering
Information” on page 64 for complete ordering
information.
The CS42448 is ideal for audio systems requiring wide
dynamic range, negligible distortion and low noise, such
as A/V receivers, DVD receivers, and automotive audio
systems.
Control Port & Serial
Audio Port Supply =
1.8 V to 5 V
Digital Supply =
3.3 V to 5 V
Analog Supply =
3.3 V to 5 V
I2C/SPI
Software Mode
Control Data
Interrupt
Reset
Register
Configuration
ADC Overflow
& Clock Error
Interrupt
Internal Voltage
Reference
External
Mute Control
Mute
Control
Serial Audio
Input
Auxilliary Serial
Audio Input
Input Master
Clock
Serial Audio
Output
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Volume
Controls
Digital
Filters
ΔΣ
Modulators
Multibit
DAC1-4 and
8
Differential or
Single-Ended
Analog Filters
Outputs
8
High Pass
Filter
High Pass
Filter
Digital
Filters
Digital
Filters
Multibit
Oversampling
ADC1&2
Multibit
Oversampling
ADC3
4
4
2
2
*Optional MUX allows selection from up to 4 single-ended inputs.
Copyright © Cirrus Logic, Inc. 2006
(All Rights Reserved)
Differential or
Single-Ended
Analog Inputs
NOVEMBER '06
DS648F2




CS42448 pdf, 반도체, 판매, 대치품
CS42448
6.16 MUTEC Pin Control (Address 1Bh) .............................................................................................. 52
6.17 MUTEC Polarity Select (MCPOLARITY) ...................................................................................... 52
6.18 MUTE CONTROL ACTIVE (MUTEC ACTIVE) ............................................................................. 52
7. EXTERNAL FILTERS............................................................................................................................ 53
7.1 ADC Input Filter .............................................................................................................................. 53
7.1.1 Passive Input Filter ................................................................................................................ 54
7.1.2 Passive Input Filter w/Attenuation ......................................................................................... 54
7.2 DAC Output Filter ........................................................................................................................... 56
8. ADC FILTER PLOTS............................................................................................................................. 57
9. DAC FILTER PLOTS............................................................................................................................. 59
10. PARAMETER DEFINITIONS............................................................................................................... 61
11. REFERENCES..................................................................................................................................... 62
12. PACKAGE INFORMATION................................................................................................................. 63
12.1 Thermal Characteristics ............................................................................................................... 63
13. ORDERING INFORMATION ............................................................................................................... 64
14. REVISION HISTORY ........................................................................................................................... 64
LIST OF FIGURES
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Figure 1.Typical Connection Diagram ......................................................................................................... 9
Figure 2.Output Test Circuit for Maximum Load ....................................................................................... 16
Figure 3.Maximum Loading ....................................................................................................................... 16
Figure 4.Serial Audio Interface Slave Mode Timing .................................................................................. 18
Figure 5.TDM Serial Audio Interface Timing ............................................................................................. 18
Figure 6.Serial Audio Interface Master Mode Timing ................................................................................ 19
Figure 7.Serial Audio Interface Slave Mode Timing .................................................................................. 20
Figure 8.Control Port Timing - I²C Format ................................................................................................. 21
Figure 9.Control Port Timing - SPI Format ................................................................................................ 22
Figure 10.Full-Scale Input ......................................................................................................................... 25
Figure 11.ADC3 Input Topology ................................................................................................................ 25
Figure 12.Audio Output Initialization Flow Chart ....................................................................................... 27
Figure 13.Full-Scale Output ...................................................................................................................... 29
Figure 14.De-Emphasis Curve .................................................................................................................. 30
Figure 15.I²S Format ................................................................................................................................. 32
Figure 16.Left Justified Format ................................................................................................................. 32
Figure 17.Right Justified Format ............................................................................................................... 32
Figure 18.One-Line Mode #1 Format ........................................................................................................ 32
Figure 19.One Line Mode #2 Format ........................................................................................................ 33
Figure 20.TDM Format .............................................................................................................................. 33
Figure 21.AUX I²S Format ......................................................................................................................... 34
Figure 22.AUX Left-Justified Format ......................................................................................................... 35
Figure 23.Control Port Timing in SPI Mode .............................................................................................. 36
Figure 24.Control Port Timing, I²C Write ................................................................................................... 36
Figure 25.Control Port Timing, I²C Read ................................................................................................... 37
Figure 26.Single to Differential Active Input Filter ..................................................................................... 53
Figure 27.Single-Ended Active Input Filter ................................................................................................ 53
Figure 28.Passive Input Filter ................................................................................................................... 54
Figure 29.Passive Input Filter w/Attenuation ............................................................................................. 55
Figure 30.Active Analog Output Filter ....................................................................................................... 56
Figure 31.Passive Analog Output Filter .................................................................................................... 56
Figure 32.SSM Stopband Rejection .......................................................................................................... 57
Figure 33.SSM Transition Band ................................................................................................................ 57
Figure 34.SSM Transition Band (Detail) ................................................................................................... 57
Figure 35.SSM Passband Ripple .............................................................................................................. 57
4 DS648F2

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CS42448 전자부품, 판매, 대치품
DAC_SDIN1
DAC_SDIN2
DAC_SDIN3
DAC_SDIN4
DAC_SCLK
DAC_LRCK
AUX_LRCK
AUX_SCLK
AUX_SDIN
AOUT1 +,-
AOUT2 +,-
AOUT3 +,-
AOUT4 +,-
AOUT5 +,-
AOUT6 +,-
AOUT7 +,-
AOUT8 +,-
AGND
VQ
VAwww.DataSheet4U.com
AIN1 +,-
AIN2 +,-
AIN3 +,-
AIN4 +,-
AIN5 +,-
AIN6 +,-
AIN5 A,B
AIN6 A,B
MUTEC
FILT+_DAC
FILT+_ADC
INT
SCL/CCLK
SDA/CDOUT
CS42448
17
16
15
DAC Serial Audio Data Input (Input) - Input for two’s complement serial audio data.
14
18
DAC Serial Clock (Input/Output) - Serial clock for the DAC serial audio interface. Input frequency
must be 256xFs in the TDM digital interface format.
DAC Left/Right Clock (Input/Output) - Determines which channel, Left or Right, is currently
19 active on the DAC serial audio data line. Signals the start of a new TDM frame in the TDM digital
interface format.
20
Auxiliary Left/Right Clock (Output) - Determines which channel, Left or Right, is currently active
on the Auxiliary serial audio data line. Derived from the ADC serial port and equals Fs.
21 Auxiliary Serial Clock (Output) - Serial clock for the Auxiliary serial audio interface.
22
Auxiliary Serial Input (Input) - Provides an additional serial input for two’s complement serial
audio data. Used only in the TDM digital interface format.
26,25
27,28
30,29
31,32 Differential Analog Output (Output) - The full-scale analog output level is specified in the Analog
34,33 Characteristics table. Each leg of the differential outputs may also be used single-ended.
36,37
39,38
40,41
42,56 Analog Ground (Input) - Ground reference for the analog section
43 Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage.
44,53
Analog Power (Input) - Positive power supply for the analog section. See “Digital I/O Pin Charac-
teristics” on page 8.
46,45
48,47
50,49
52,51
58,57
Differential Analog Input (Input) - Signals are presented differentially or single-ended to the
delta-sigma modulators. The full-scale input level is specified in the Analog Characteristics speci-
fication table. See below for a description of AIN5-AIN6 in Single-Ended Mode.
60,59
Single-Ended Analog Input (Input) - When stereo ADC3 is in Single-Ended Mode, an internal
58,57 analog mux allows selection between 2 channels for both analog inputs AIN5 and AIN6 (see Sec-
60,59 tion 4.2.3 on page 26 for details). The unused leg of each input is internally connected to common
mode. The full-scale input level is specified in the Analog Characteristics table.
35
Mute Control (Output) - Used as a control for external mute circuits to prevent the clicks and
pops that can occur in any single supply system.
54
Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling cir-
cuits of the DAC.
55
Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling cir-
cuits of the ADC.
61
Interrupt (Output) - Signals either an ADC overflow condition has occurred in one or more of the
ADC inputs, or a clocking error has occurred in the DAC/ADC as specified in the Interrupt register.
63 Serial Control Port Clock (Input) - Serial clock for the control port interface.
64 Serial Control Data I/O (Input/Output) - Input/Output for I²C data. Output for SPI data.
DS648F2
7

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