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BUF12800 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 BUF12800
기능 REFERENCE VOLTAGE GENERATOR
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BUF12800 데이터시트, 핀배열, 회로
BUF12800
SBOS315 − DECEMBER 2004
REFERENCE VOLTAGE GENERATOR
for LCD GAMMA CORRECTION
FEATURES
D 12-CHANNEL GAMMA CORRECTION
D 10-BIT RESOLUTION
D DOUBLE-BUFFERED DAC REGISTERS
D INTEGRATED REFERENCE BUFFERS
D RAIL-TO-RAIL OUTPUT
D LOW SUPPLY CURRENT: 900µA/ch
D SUPPLY VOLTAGE: 7V to 18V
D DIGITAL SUPPLY: 2.7V to 5.5V
D INDUSTRY-STANDARD TWO-WIRE INTERFACE
− High-Speed Mode: 3.4MHz
D HIGH ESD RATING:
− 4kV HBM, 1kV CDM, 200V MM
D DEMOBOARD AND SOFTWARE AVAILABLE
www.DataSheet4U.com
VSD
4
VS
1, 2
BUF12800
REFH
3
6
SDA
SCL
5
Control IF
87
LD A0
10
REFL
9
13
Out A
14
Out B
15
Out C
16
Out D
17
Out E
18
Out F
19
Out G
20
Out H
21
Out I
22
Out J
23
Out K
24
Out L
11, 12
APPLICATIONS
D TFT-LCD REFERENCE DRIVERS
D REFERENCE VOLTAGE GENERATORS
D INDUSTRIAL PROCESS CONTROL
DESCRIPTION
The BUF12800 is a programmable voltage reference
generator designed for dynamic gamma correction in
TFT-LCD panels. It provides 12 programmable outputs,
each with 10-bit resolution.
TI’s new, small geometry, state-of-the-art, analog CMOS
process allows the use of one digital-to-analog converter
(DAC) per channel while still maintaining a very small chip
size. This topology has the advantage of significantly
increased programming speed over existing program-
mable buffers.
Programming of each output occurs through an industry-
standard, two-wire serial interface. Unlike existing
programmable buffers, the BUF12800 offers a high-
speed, two-wire interface mode that allows clock speeds
up to 3.4MHz. The BUF12800 features a double-buffered
DAC register structure that significantly simplifies imple-
mentation of dynamic gamma control. This further reduces
programming time, especially when many channels have
to be updated simultaneously.
Reference pins set the high and low voltages of the output
range. They are internally buffered, which simplifies
design. They may be connected to external resistors to
divide the output range for finer resolution of outputs.
The BUF12800 is available in a TSSOP-24 PowerPAD
package. It is specified from −40°C to +85°C.
BUF12800 RELATED PRODUCTS
FEATURES
11-Channel Gamma Correction Buffer, Int VCOM
6-Channel Gamma Correction Buffer, Int VCOM
6-Channel Gamma Correction Buffer
4-Channel Gamma Correction Buffer, Int VCOM
High-Supply Voltage Gamma Buffers
20-Channel Programmable Buffer, 10-Bit, VCOM
PRODUCT
BUF11702
BUF07703
BUF06703
BUF05703
BUFxx704
BUF20800
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright 2004, Texas Instruments Incorporated
www.ti.com




BUF12800 pdf, 반도체, 판매, 대치품
BUF12800
SBOS315 − DECEMBER 2004
www.ti.com
TYPICAL CHARACTERISTICS
At TA = +25°C, VS = 18V, VSD = 5V, VREFH = 17V, VREFL = 1V, RL = 1.5kconnected to ground, and CL = 200pF, unless otherwise noted.
ANALOG SUPPLY CURRENT vs TEMPERATURE
10
VS = 18V
8
VS = 10V
6
4
2
0
40 20
0
20 40 60 80 100
Temperature (_ C)
Figure 1
FULL−SCALE OUTPUT SWING
REFH = 17V
REFL = 1V
Code 3FF 000
Code 000 3FF
Time (1µs/div)
Figure 3
INTEGRAL NONLINEARITY ERROR vs INPUT CODE
0.6
0.4
0.2
0
0.2
0.4
0.6
0
200 400 600 800 1000
Input Code
Figure 5
4
DIGITAL SUPPLY CURRENT vs TEMPERATURE
30
VS = 10V
25
VSD = 5V
20
15
VSD = 3.3V
10
5
0
40 20
0
20 40 60 80 100
Temperature (_ C)
Figure 2
OUTPUT VOLTAGE vs OUTPUT CURRENT
18
Channel A (sourcing), Code = 3FFh
VREFL = 1V, VREFH = 17.8V
17 RLOAD Connected to GND
Channel L (sourcing), Code = 3FFh
16 VREFL = 0.2V, VREFH = 17V
RLOAD Connected to GND
Channel L (sinking), Code = 000h
2 Channel A (sinking), Code = 000h
VREFL = 1V, VREFH = 17.8V
RLOAD Connected to 18V
1
VREFL = 0.2V, VREFH = 17V
RLOAD Connected to 18V
0
0 10 20 30 40 50 60 70 80 90 100
Output Current (mA)
Figure 4
DIFFERENTIAL NONLINEARITY ERROR vs INPUT CODE
0.6
0.4
0.2
0
0.2
0.4
0.6
0
200 400 600 800 1000
Input Code
Figure 6

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BUF12800 전자부품, 판매, 대치품
BUF12800
www.ti.com
READ/WRITE OPERATIONS
The BUF12800 is able to read from a single DAC or
multiple DACs, or write to the register of a single DAC, or
multiple DACs in a single communication transaction.
DAC addresses begin with 0000, which corresponds to
DAC_A, through 1011, which corresponds to DAC_L.
Write commands are performed by setting the read/write
bit LOW. Setting the read/write bit HIGH will perform a read
transaction.
Writing
To write to a single DAC register:
1. Send a START condition on the bus.
2. Send the device address and read/write bit = LOW.
The BUF12800 will acknowledge this byte.
3. Send a DAC address byte. Bits D7−D4 are unused
and should be set to 0. Bits D3−D0 are the DAC
address. Only DAC addresses 0000 to 1011 are valid
and will be acknowledged.
4. Send two bytes of data for the specified DAC. Begin
by sending the most significant byte first (bits D15−D8,
of which only bits D9 and D8 are used), followed by the
least significant byte (bits D7−D0). The DAC register
is updated after receiving the second byte.
5. Send a STOP condition on the bus.
The BUF12800 will acknowledge each data byte. If the
master terminates communication early by sending a
STOP or START condition on the bus, the specified
register will not be updated. Updating the DAC register is
not the same as updating the DAC output voltage. See the
Output Latch section.
The process of updating multiple registers begins the
same as when updating a single register. However,
instead of sending a STOP condition after writing the
addressed register, the master will continue to send data
for the next register. The BUF12800 will automatically and
sequentially step through subsequent registers as addi-
tional data is sent. The process will continue until all de-
sired registers have been updated or a stop condition is
sent.
To write to all registers:
1. Send a START condition on the bus.
2. Send the device address and read/write bit = LOW.
The BUF12800 will acknowledge this byte.
3. Send either the DAC_A address byte to start at the
first DAC or send the address of whichever DAC will
be the first to be updated. The BUF12800 will begin
with this DAC and step through subsequent DACs in
sequential order.
4. Send 24 bytes of data. The first two bytes are for
DAC_A. It is automatically updated after receiving the
second byte. The next two are for DAC_B. The DAC
register is updated after receiving the fourth byte. The
last two bytes are for DAC_L. The DAC register is
updated after receiving the 24th byte. For each DAC,
SBOS315 − DECEMBER 2004
begin by sending the most significant byte (bits
D15−D8, of which only bits D9 and D8 have meaning),
followed by the least significant byte (bits D7−D0).
5. Send a STOP condition on the bus.
The BUF12800 will acknowledge each byte. To terminate
communication, send a Stop or Start condition on the bus.
Only DACs that have received both bytes will be updated.
Reading
To read the registers of one DAC:
1. Send a START condition on the bus.
2. Send the device address and read/write bit = LOW.
The BUF12800 will acknowledge this byte.
3. Send a DAC address byte. Bits D7−D4 have no
meaning; Bits D3−D0 are the DAC address. Only DAC
addresses 0000 to 1011 are valid and will be
acknowledged.
4. Send a START or STOP/START condition on the bus.
5. Send correct device address and read/write
bit = HIGH. The BUF12800 will acknowledge this
byte.
6. Receive two bytes of data. They are for the specified
DAC. The first received byte is the most significant
byte (bits D15−D8, of which only bits D9 and D8 have
meaning); the next is the least significant byte (bits
D7−D0).
7. Acknowledge after receiving each byte.
8. Send a STOP condition on the bus.
Communication may be terminated by sending a
premature STOP or START condition on the bus, or by not
sending the acknowledge.
To read all DAC registers:
1. Send a START condition on the bus.
2. Send the device address and read/write bit = LOW.
The BUF12800 will acknowledge this byte.
3. Send the DAC_A address byte to start at the first DAC.
4. Send the device address and read/write bit = HIGH.
5. Receive 24 bytes of data. The first two bytes are for
DAC_A. The next two are for DAC_B. The last two
bytes are for DAC_L. For each DAC, the first received
byte is the most significant byte (bits D15−D8, of
which only bits D9 and D8 have meaning). The next
byte is the least significant byte (bits D7−D0).
6. Acknowledge after receiving each byte.
7. Send a STOP condition on the bus.
Communication may be terminated by sending a
premature STOP or START condition on the bus, or by not
sending the acknowledge.
7

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관련 데이터시트

부품번호상세설명 및 기능제조사
BUF12800

REFERENCE VOLTAGE GENERATOR

Burr-Brown
Burr-Brown
BUF12800

Reference Voltage Generator for LCD Gamma Correction (Rev. D)

Texas Instruments
Texas Instruments

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