PDF MC33874 Data sheet ( Hoja de datos )

Número de pieza	MC33874
Descripción	Quad High-Side Switch
Fabricantes	Freescale Semiconductor
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No Preview Available ! Freescale Semiconductor Advance Information Document Number: MC33874 Rev. 8.0, 4/2007 Quad High-Side Switch (Quad 35 mΩ) 33874 The 33874 is one in a family of devices designed for low-voltage automotive and industrial lighting and motor control applications. Its four low RDS(ON) MOSFETs (four 35 mΩ) can control the high sides of four separate resistive or inductive loads. Programming, control, and diagnostics are accomplished using a 16-bit SPI interface. Additionally, each output has its own parallel input for pulse-width modulation (PWM) control if desired. The 33874 allows the user to program via the SPI the fault current trip levels and duration of acceptable lamp inrush or motor stall intervals. Such programmability allows tight control of fault currents and can protect wiring harnesses and circuit boards as well as loads. HIGH-SIDE SWITCH The 33874 is packaged in a power-enhanced 12x 12 nonleaded Power QFN package with exposed tabs. Features www.DataSheet4U.com • Quad 35 mΩ High-Side Switches (at 25°C) • Operating Voltage Range of 6.0 V to 27 V with Standby Current < 5.0 µA • SPI Control of Overcurrent Limit, Overcurrent Fault Blanking Time, Output OFF Open Load Detection, Output ON/OFF Control, Watchdog Timeout, Slew Rates, and Fault Status Reporting • SPI Status Reporting of Overcurrent, Open and Shorted Loads, Overtemperature, Undervoltage and Overvoltage Shutdown, Fail-Safe Pin Status, and Program Status • Analog Current Feedback with Selectable Ratio • Analog Board Temperature Feedback • Enhanced -16 V Reverse Polarity VPWR Protection • Pb-Free Packaging Designated by Suffix Code PNA PNA SUFFIX (PB_FREE) 98ARL10596D 24-PIN PQFN (12 x 12) ORDERING INFORMATION Device MC33874BPNA/R2 Temperature Range (TA) -40°C to 125°C Package 24 PQFN VDD VDD VPWR VDD VPWR 33874 VDD VPWR SO SCLK CS SI I/O MCU I/O I/O I/O I/O I/O A/D GND A/D WAKE SI SCLK CS SO RST FS IN0 IN1 IN2 IN3 CSNS TEMP FSI GND HS0 HS1 HS2 HS3 LOAD 0 LOAD 1 LOAD 2 LOAD 3 Figure 1. 33874 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2006. All rights reserved. 1 page ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings Symbol Value Unit ELECTRICAL RATINGS Operating Voltage Range Steady-State VDD Supply Voltage Input/Output Voltage (1) SO Output Voltage (1) WAKE Input Clamp Current CSNS Input Clamp Current HS [0:3] Voltage Positive Negative Output Current (2) Output Clamp Energy (3) ESD Voltage (4) Human Body Model (HBM) Charge Device Model (CDM) Corner Pins (1, 13, 19, 21) All Other Pins (2-12, 14-18, 20, 22-24) VPWR(SS) VDD See note (1) VSO ICL(WAKE) ICL(CSNS) VHS IHS[0:3] ECL [0:3] VESD -16 to 41 -0.3 to 5.5 -0.3 to 7.0 -0.3 to VDD+0.3 2.5 10 41 -16 11 85 ± 2000 ± 750 ± 500 V V V V mA mA V A mJ V THERMAL RATINGS Operating Temperature °C Ambient Junction Storage Temperature Thermal Resistance (5) Junction to Case Junction to Ambient TA TJ TSTG RθJC RθJA -40 to 125 -40 to 150 -55 to 150 <1.0 30 °C °C/ W Peak Pin Reflow Temperature During Solder Mounting (6) TSOLDER 240 °C Notes 1. Exceeding voltage limits on IN[0:3], RST, FSI, CSNS, TEMP, SI, SO, SCLK, CS, or FS pins may cause a malfunction or permanent damage to the device. 2. Continuous high-side output current rating so long as maximum junction temperature is not exceeded. Calculation of maximum output current using package thermal resistance is required. 3. Active clamp energy using single-pulse method (L = 2 mH, RL = 0 Ω, VPWR = 14 V, TJ = 150°C initial). 4. ESD testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), Charge Device Model (CDM), Robotic (CZAP = 4.0 pF). 5. Device mounted on a 2s2p test board per JEDEC JESD51-2. 6. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Analog Integrated Circuit Device Data Freescale Semiconductor 33874 5 5 Page ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 27 V, 4.5 V ≤ VDD ≤ 5.5 V, -40°C ≤ TA ≤ 125°C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit POWER OUTPUT TIMING (HS0, HS1, HS2, HS3) (continued) Overcurrent High Detection Blanking Time CS to CSNS Valid Time (24) Watchdog Timeout (25) WD[1:0] : 00 WD[1:0] : 01 WD[1:0] : 10 WD[1:0] : 11 Direct Input Switching Frequency (DICR D3 = 0) SPI INTERFACE CHARACTERISTICS (RST, CS, SCLK, SI, SO) tOCH t CNSVAL t WDTO0 t WDTO1 t WDTO2 t WDTO3 fPWM 1.0 – 446 223 1800 900 - 5.0 – 558 279 2250 1125 300 20 10 725 363 2925 1463 - µs µs ms Hz Maximum Frequency of SPI Operation Required Low State Duration for RST (26) Rising Edge of CS to Falling Edge of CS (Required Setup Time) (27) Rising Edge of RST to Falling Edge of CS (Required Setup Time) (27) Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) (27) Required High State Duration of SCLK (Required Setup Time) (27) Required Low State Duration of SCLK (Required Setup Time) (27) Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) (27) SI to Falling Edge of SCLK (Required Setup Time) (28) Falling Edge of SCLK to SI (Required Setup Time) (28) SO Rise Time CL = 200 pF SO Fall Time CL = 200 pF SI, CS, SCLK, Incoming Signal Rise Time (28) SI, CS, SCLK, Incoming Signal Fall Time (28) Time from Falling Edge of CS to SO Low Impedance (29) Time from Rising Edge of CS to SO High Impedance (30) Time from Rising Edge of SCLK to SO Data Valid (31) 0.2 VDD ≤ SO ≤ 0.8 VDD, CL = 200 pF f SPI t WRST t CS t ENBL t LEAD t WSCLKh t WSCLKl t LAG t SI (SU) t SI (HOLD) t RSO t FSO t RSI t FSI t SO(EN) t SO(DIS) t VALID – – – – – – – – – – – – – – – – – – 3.0 MHz 50 350 ns – 300 ns – 5.0 µs 50 167 ns – 167 ns – 167 ns 50 167 ns 25 83 ns 25 83 ns ns 25 50 ns 25 50 – 50 ns – 50 ns – 145 ns 65 145 ns ns 65 105 Notes 24. Time necessary for the CSNS to be with ±5% of the targeted value. 25. Watchdog timeout delay measured from the rising edge of WAKE or RST from a sleep state condition, to output turn-ON with the output driven OFF and FSI floating. The values shown are for WDR setting of [00]. The accuracy of tWDTO is consistent for all configured watchdog timeouts. 26. RST low duration measured with outputs enabled and going to OFF or disabled condition. 27. Maximum setup time required for the 33874 is the minimum guaranteed time needed from the microcontroller. 28. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. 29. Time required for output status data to be available for use at SO. 1.0 kΩ on pullup on CS. 30. Time required for output status data to be terminated at SO. 1.0 kΩ on pullup on CS. 31. Time required to obtain valid data out from SO following the rise of SCLK. Analog Integrated Circuit Device Data Freescale Semiconductor 33874 11 11 Page

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