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PDF MC34703 Data sheet ( Hoja de datos )
| Número de pieza | MC34703 | |
| Descripción | Switch-Mode Power Supply | |
| Fabricantes | Freescale Semiconductor | |
| Logotipo |  |
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Freescale Semiconductor
Technical Data
10A+ Switch-Mode Power
Supply with LDO Regulator
Document Number: MC34703
Rev. 5.0, 8/2006
34703
The 34703 integrated power supply IC is designed to support the
PowerQUICC™ family of MCUs as well as other MCUs and DSPs
requiring a high current core supply. The 34703 incorporates a high-
performance switching regulator for the microprocessor’s core
supply, and a low-dropout (LDO) linear regulator control circuit to
provide I/O and bus voltage.
The switching regulator is an efficient synchronous buck converter
with integrated low RDS(ON) high side and low side FETs.
Temperature and current sensing is built in and provides protection
for the IC as well as the external circuitry.
The 34703 incorporates specific advanced protection features for
use with high power processors and controllers, including power-up
and power-down sequencing of the I/O and core supply voltages in
relation to each other.
INTEGRATED POWER SUPPLY IC
Features
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www.DataSheet4U.com
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Wide input Operating Voltage Range: 2.8 V to 13.5 V
Adjustable Output Voltages
Continuous Core Voltage Supply Currents up to 10 A (with
infrequent excursions to 12 A permitted)
Undervoltage Lockout
Selectable Power Sequencing
Programmable Watchdog Timer
Voltage Margining via I2C Bus
Overcurrent Protection
Reset with Programmable Power-ON Delay
PNB SUFFIX
98ASA10705D
33-PIN PQFN
ORDERING INFORMATION
Device
Temperature
Range (TA)
Package
MC34703PNB/R2 -40 to 85°C
33 PQFN
2.8 to 13.5 V
I2C
Bus
Optional
34703
VIN2
VBST
VBST (sense)
VBD
FREQ
CLKSYN
SDA
SCL
EN1
EN2
CLKSEL
ADDR
VDDI
VIN1
LDRV
ISNS
LDO
LCMP
SR
LFB
RESET
BOOT
SW_A
SW_B
VOUT
COMP
INV
RT
MCU
VDDH (I/O)
POR
VBST
VDDL (Core)
Figure 1. MC34703 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2006. All rights reserved.
1 page  
PIN CONNECTIONS
Table 1. 34703 Pin Definitions (continued)
A functional description of each pin can be found in the Functional Pin Description section beginning on page 15.
Pin Number Pin Name Pin Function Formal Name
Definition
25, 31
These pins are not present in package.
26 NC Heatsink
No electrical connection, thermal heatsinking only.
27, 28 SW Output
Switch
Buck regulator switching node. This pin is connected to the high power
inductor.
29
PGND
Power
Power Ground
Buck regulator and Power Sequencing shunt FETs Power Ground.
30
VIN2
Input
Input Voltage 2
Buck regulator power input. Drain of the high-side power MOSFET.
32
BOOT
Input
Bootstrap
Bootstrap capacitor input.
33
SR Passive
Slew Rate
Buck converter Slew Rate control pin.
Analog Integrated Circuit Device Data
Freescale Semiconductor
34703
5
5 Page 
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions -40°C ≤ TJ ≤ 125°C unless otherwise noted. Input voltages VIN1 = VIN2 = 3.3 V using
the typical application circuit (see Figure 27) unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max Unit
BUCK CONVERTER (SW, SR)
Duty Cycle Range (Normal Operation) (22)
D 10 – 90 %
Switching Node SW Rise Time (22)
ILOAD = 10 A, SR = OPEN, VIN1 = VIN2 = 3.3 V
tROPEN
– 10 –
Switching Node SW Fall Time (22)
ILOAD = 10 A, SR = OPEN, VIN1 = VIN2 = 3.3 V
tFOPEN
– 10 –
Switching Node SW Rise Time (22)
ILOAD = 10 A, SR = SW, VIN1 = VIN2 = 3.3 V
tRSW
– 14 –
Switching Node SW Fall Time (22)
ILOAD = 10 A, SR = SW, VIN1 = VIN2 = 3.3 V
tFSW
– 14 –
Switching Node SW Rise Time (22)
ILOAD = 10 A, SR = BOOT,VIN1 = VIN2 = 3.3 V
tRBOOT
– 6.0 –
Switching Node SW Fall Time (22)
ILOAD = 10 A, SR = BOOT, VIN1 = VIN2 = 3.3 V
tFBOOT
– 6.0 –
Maximum Deadtime (22)
tD – 150 –
Buck Control Loop Propagation Delay (22)
VINV < 0.8 V to VSW > 90% of High Level or VINV > 0.8 V to VSW < 10%
of Low Level
tPD
– 50
–
ns
ns
ns
ns
ns
ns
ns
ns
Soft Start Duration (Power Sequencing Disabled, EN1 = 1, EN2 = 1) (22)
tSS
800 µs
Fault Condition Timeout (22)
tFAULT
–
10
–
ms
Retry Timer Cycle (22)
tRET
– 100 –
ms
OSCILLATOR (FREQ)
Oscillator Default Frequency (Switching Frequency), FREQ Pin Open
fOSC 250 300 350 kHz
Oscillator Frequency Range
fOSC
200
400 kHz
Oscillator Output Signal Duty Cycle (Square Wave, 180° Out-of-Phase with
DOSC
%
the Internal Suitable Oscillator) (23)
– 50 –
Synchronization Pulse Minimum Duration (22)
tSYNC
300
–
– ns
BOOST REGULATOR (VBST, VBST (sense), VBD)
Boost Regulator FET Maximum ON Time (23)
Boost Regulator Control Loop Propagation Delay (22)
Boost Switching Node VBD Rise Time (22)
IBST = 45 mA
Boost Switching Node VBD Fall Time (22)
IBST = 45 mA
tON – 24 – µs
tBSTPD
–
50
–
ns
tBR ns
– 35 –
tBF ns
– 5.0 –
Notes
22. Design Information only. Not production tested.
23. Not production tested for typical values specified.
Analog Integrated Circuit Device Data
Freescale Semiconductor
34703
11
11 Page | ||
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