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PDF MR0A16A Data sheet ( Hoja de datos )
| Número de pieza | MR0A16A | |
| Descripción | 64K x 16-Bit 3.3-V Asynchronous Magnetoresistive RAM | |
| Fabricantes | Freescale Semiconductor | |
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Freescale Semiconductor
Data Sheet: Advance Information
Document Number: MR0A16A
Rev. 0, 6/2007
64K x 16-Bit 3.3-V
Asynchronous
Magnetoresistive RAM
MR0A16A
44-TSOP
Case 924A-02
Introduction
The MR0A16A is a 1,048,576-bit magnetoresistive
random access memory (MRAM) device
organized as 65,536 words of 16 bits. The
www.DataSheet4U.com
MR0A16A is equipped with chip enable (E), write
enable (W), and output enable (G) pins, allowing
for significant system design flexibility without bus
contention. Because the MR0A16A has separate
byte-enable controls (LB and UB), individual bytes
can be written and read.
MRAM is a nonvolatile memory technology that
protects data in the event of power loss and does
not require periodic refreshing. The MR0A16A is
the ideal memory solution for applications that
must permanently store and retrieve critical data
quickly.
The MR0A16A is available in a 400-mil, 44-lead
plastic small-outline TSOP type-II package with an
industry-standard center power and ground SRAM
pinout.
The MR0A16A is available in Commercial (0˚C to
70˚C), Industrial (-40˚C to 85˚C) and Extended
(-40˚C to 105˚C) ambient temperature ranges.
Features
• Single 3.3-V power supply
• Commercial temperature range (0˚C to
70˚C), Industrial temperature range (-40˚C
to 85˚C) and Extended temperature range
(-40˚C to 105˚C)
• Symmetrical high-speed read and write with
fast access time (35 ns)
• Flexible data bus control — 8 bit or 16 bit
access
• Equal address and chip-enable access
times
• Automatic data protection with low-voltage
inhibit circuitry to prevent writes on power
loss
• All inputs and outputs are
transistor-transistor logic (TTL) compatible
• Fully static operation
• Full nonvolatile operation with 20 years
minimum data retention
This document contains information on a new product under development. Freescale
reserves the right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2007. All rights reserved.
1 page  
Direct Current (dc)
Electrical Specifications
Parameter
Input leakage current
Output leakage current
Output low voltage
(IOL = +4 mA)
(IOL = +100 μA)
Output high voltage
(IOH = –4 mA)
(IOH = –100 mA)
Table 5. dc Characteristics
Symbol
Min
Typ
Max Unit
Ilkg(I)
—
—
±1 μA
Ilkg(O)
—
—
±1 μA
VOL —
— 0.4 V
VSS + 0.2
VOH
2.4
VDD – 0.2
—
—V
Table 6. Power Supply Characteristics
Parameter
ac active supply current — read modes1
(IOut = 0 mA, VDD = max)
ac active supply current — write modes1
(VDD = max)
ac standby current
(VDD = max, E = VIH)
(no other restrictions on other inputs)
Symbol
IDDR
IDDW
ISB1
Typ
TBD
TBD
TBD
CMOS standby current
(E ≥ VDD – 0.2 V and VIn ≤ VSS + 0.2 V or ≥ VDD – 0.2 V)
(VDD = max, f = 0 MHz)
ISB2
TBD
NOTES:
1 All active current measurements are measured with one address transition per cycle.
Max
TBD
TBD
TBD
TBD
Unit
mA
mA
mA
mA
Table 7. Capacitance1
Parameter
Symbol
Typ
Max
Address input capacitance CIn —
6
Control input capacitance
CIn —
6
Input/output capacitance
CI/O
—
8
NOTES:
1 f = 1.0 MHz, dV = 3.0 V, TA = 25˚C, periodically sampled rather than 100% tested.
Unit
pF
pF
pF
Freescale Semiconductor
MR0A16A Advanced Information Data Sheet, Rev. 0
5
5 Page 
Timing Specifications
Table 11. Write Cycle Timing 2 (E Controlled)1, 2, 3, 4, 5
Parameter
Symbol Min Max Unit
Write cycle time6
tAVAV 35 — ns
Address set-up time
tAVEL 0 — ns
Address valid to end of write (G high)
tAVEH 18 — ns
Address valid to end of write (G low)
tAVEH 20 — ns
Enable to end of write (G high)
tELEH
tELWH
15
—
ns
Enable to end of write (G low)7, 8
tELEH
tELWH
15
—
ns
Data valid to end of write
tDVEH 10 — ns
Data hold time
tEHDX 0 — ns
Write recovery time
tEHAX 12 — ns
NOTES:
1 A write occurs during the overlap of E low and W low.
2 Due to product sensitivities to noise, power supplies must be properly grounded and decoupled
and bus contention conditions must be minimized or eliminated during read and write cycles.
3 If G goes low at the same time or after W goes low, the output will remain in a high-impedance
state.
4 After W, E, or UB/LB has been brought high, the signal must remain in steady-state high for a
minimum of 2 ns.
5 The minimum time between E being asserted low in one cycle to E being asserted low in a
subsequent cycle is the same as the minimum cycle time allowed for the device.
6 All write cycle timings are referenced from the last valid address to the first transition address.
7 If E goes low at the same time or after W goes low, the output will remain in a high-impedance
state.
8 If E goes high at the same time or before W goes high, the output will remain in a high-impedance
state.
Freescale Semiconductor
MR0A16A Advanced Information Data Sheet, Rev. 0
11
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